Abstract: A rules-based mechanism is described for powering down racks in an ordered and autonomous way in a data center. Power shelf controllers (PSCs), on different racks or on the same rack, communicate together through a network, called the PSC network, separate from the data network. The PSCs are aware of the other PSCs that share the same input power domain. When the racks are configured for use, each PSC is assigned a priority value, based upon the management provisioning layer assignment. Each PSC creates a table of all the other PSCs and tracks each assigned priority value. When a power event occurs, the PSC can power down components within the rack in accordance with the priority table. Recovery can also be carried out in conformance with the priority table.

Abstract: When a computer boots up, a Basic Input/Output System (BIOS) configures system memory to have a crash memory area within the system address map, which can be used by a processor to dump crash memory data. When an error event occurs, the processor can initiate a dump to the crash memory area. Any desired data can be placed into the crash memory area, but typical data can include a state of registers in the processor. The processor then sets a flag, such as an external pin, indicating that the crash memory data is ready to be read. The flag can be read by a secure processor, which then reads the crash memory area at normal memory access speeds using the system bus. For example, the secure processor can access the crash memory area using Direct Memory Access (DMA) reads over a PCIe system bus.

Abstract: Firmware modules for a plurality of computer components of a computer system can be downloaded from an external computer system via a network connection. The firmware modules can be stored in a firmware memory of the computer system. During booting or at other appropriate times, the plurality of computer components can access the firmware memory to obtain their respective firmware modules.

Abstract: Provided are systems and methods for enabling peer-to-peer communications between peripheral devices. In various implementations, a computing system can include a PCI switch device. The first PCI switch device can include a first port and be communicatively coupled to a first root complex port. The first PCI switch device can have access to a first PCI endpoint address range. The computing system can further include a second PCI switch device. The second PCI switch device can include a second port, connected to the first port. The second PCI switch device can be communicatively coupled to a second root complex port that is different from the first root complex port. The second PCI switch device can receive a transaction addressed to the first PCI endpoint address range, and identify the transaction as associated with the second port. The second PCI switch device can subsequently transmit the transaction using the second port.

Abstract: Systems and methods for an integrated reliability, availability, and serviceability (RAS) state machine are provided. Handling of RAS events by the Basic Input Output System (BIOS) of an integrated circuit device can result in lost processing time on the processing cores of a multi-core processor resulting from numerous system management interrupts generated by the BIOS. To reduce lost processing time, a dedicated state machine can execute instructions to handle RAS events independently of the BIOS and minimize the number of system management interrupts.

Abstract: Technologies are provided for determining an identity of a hardware device that transmitted an error message via a communication bus. A chipset of the communication bus can be configured to transmit an interrupt to an interrupt handler in response to receipt of the error message. The interrupt handler can be configured to determine an identity of the hardware device based on the contents of the error message. The interrupt handler can be configured to transmit a notification to an error remediation service, wherein the notification is associated with the identity of the hardware device. The remediation service can be configured to use the identity of the hardware device to perform one or more error remediation operations. In at least some embodiments, the interrupt handler is configured to store the identifier in a memory and the error remediation service is configured to retrieve the identifier from the memory.

Abstract: Provided are systems and methods for hardware attestation. Hardware attestation can ensure that only trusted hardware components are being used in a computing system. In various implementations, the computing system can include a hardware component coupled to the motherboard, where the hardware component is independent of the main processor of the computing system. The hardware component can determine whether a particular component connected to the motherboard includes an identification code, where the identification code can be used to attest to an identity of the particular component. The hardware component can further determining whether the identification code matches an expected value. The hardware component can further configure the particular component based on whether the identification code matches the expected value.

Abstract: A smart add-in card can be leveraged to perform testing on a host server computer. The add-in card can include an embedded processor and memory. Tests can be downloaded to the add-in card to test analog features of a communication bus between the host server computer (motherboard) and the add-in card. In a particular example, a PCIe communication bus couples the motherboard to the add-in card and the tests can test a connection or communication link negotiated between the add-in card and another device using the PCIe communication bus. The tests can be developed to test errors that are typically difficult to test without the use of special hardware. However, the smart add-in card can be a simple Network Interface Card (NIC) that resides on the host server computer during normal operation and is used for communication other than error testing.

Abstract: The following description is directed to dynamically adjusting a refresh rate. In one example, a method can include determining a rate of memory errors, and dynamically adjusting a refresh rate of a memory based at least partially on the determined rate of memory errors.

Abstract: In a provider network, a request is received for diagnostic information for a computing resource. In response to the request, diagnostic information from the computing resource is accessed via an out-of-band communication channel. The diagnostic information is stored for fault analysis. The out-of-band communication channel is operative when the one computing resource is not in a normal operating state.

Abstract: A management controller may request units of diagnostic information from a BIOS of the management controller's host computing device. The management controller may trigger an interrupt, in response to which the BIOS, by the execution of a processor of the host, may cause the diagnostic information to be copied to a video memory of the management controller. Upon the completion of the interrupt handler, a graphics controller of the management controller may cause the diagnostic information to be transferred to a non-volatile memory, and transferred out-of-band to a client device.

Abstract: A system is described wherein power degradation can be used in conjunction with predictive failure analysis in order to accurately determine when a hardware component might fail. In one example, printed circuit boards (PCBs) can unexpectedly malfunction due to a variety of reasons including silicon power variation or air mover speed. Other hardware components can include silicon or an integrated circuit. In order to accurately monitor the hardware component, telemetry is used to automatically receive communications regarding measurements of data associated with the hardware component, such as power-related data or temperature data. The different temperature data can include junction temperature or ambient air temperature to determine an expected power usage. The actual power usage is then compared to the expected power usage to determine whether the hardware component can soon fail.

Abstract: Self-generated thermal stress evaluation concepts are described. In one embodiment, a system includes a computing device, a cooling system, such as fans, that draws heat away from the computing device, and a management controller. The management controller can sense a temperature in the computing device and compare it against a temperature profile. The temperature profile can specify one or more target temperatures in the computing device over time. Based on the comparison, the management controller can adjust a cooling capacity of the cooling system. The adjustment to the cooling capacity can be achieved by reducing the speed of the fans, for example, to raise the temperature in the computing device. Processing tasks can also be executed in the computing device and, in response to the detection of an error in the computing device, the management controller can record the error and a profile for the error for further evaluation.

Abstract: A smart add-in card can be leveraged to perform testing on a host server computer. The add-in card can include an embedded processor and memory. Tests can be downloaded to the add-in card to test a communication bus between the host server computer (motherboard) and the add-in card. In a particular example, a PCIe communication bus couples the motherboard to the add-in card and the tests can inject errors on the PCIe communication bus. The tests can be developed to test errors that are typically difficult to test without the use of special hardware. However, the smart add-in card can be a simple Network Interface Card (NIC) that resides on the host server computer during normal operation and is used for communication other than error testing. By using the NIC as a testing device, repeatable and reliable testing can be obtained.

Abstract: A smart add-in card can be leveraged to perform testing on a host server computer. The add-in card can include an embedded processor and memory. Tests can be downloaded to the add-in card to test a protocol under which the add-in card operates. In a particular example, a PCIe communication bus couples the motherboard to the add-in card and the tests can purposely violate the PCIe specification. The tests can be developed to test conditions that are typically difficult to test without the use of special hardware. However, the smart add-in card can be a simple Network Interface Card (NIC) that resides on the host server computer during normal operation and is used for communication other than security testing. By using the NIC as a testing device, repeatable and reliable testing can be obtained.

Abstract: Provided are systems and methods for a location-aware, self-configuring peripheral device. In some implementations, the peripheral device may include two or more personalities. In these implementations, a personality enables the peripheral device to provide a service. In some implementations, the peripheral device may be configured to receive a configuration cycle. In some implementations, the peripheral device may further select a personality from among two or more personalities. The peripheral device may use information derived from the configuration cycle to make this selection. Selecting a personality may further include configuring the peripheral device according to the selected personality.

Abstract: In a cloud environment, each host computer can have its own security service processor with an independent network interface for communicating with a remote server over a network. The security service processor can provide remote management and security functionalities for various devices connected using different buses on a platform in each host computer. The security service processor can provide a centralized mechanism to verify and authenticate firmware updates for various devices using different buses. A hardware interface can allow the security service processor to provide remote debugging and diagnostic capabilities. The security service processor can also provide some of the typical functionalities of a baseboard management controller or can be used in addition to the baseboard management controller.

Abstract: Techniques and solutions for automatically filtering network broadcast traffic are described. For example, network broadcast traffic can be automatically filtered by turning broadcast filtering on and off (e.g., as a continuous strobe pattern that alternates enabling and disabling of broadcast filtering). For example, a computing device (e.g., via a network interface or management controller of the computing device) can automatically enable network broadcast traffic filtering during a first time period (e.g., a four second time period) and disable network broadcast traffic filtering during a second time period (e.g., a one second time period). A computing device can also automatically enable and disable network broadcast traffic filtering according to an on-off pattern (e.g., based on various criteria, such as network queue size, broadcast traffic volume, etc.).