Patents by Inventor Christopher Jezewski

Christopher Jezewski has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11018075
    Abstract: An example relates to an integrated circuit including a semiconductor substrate, and a wiring layer stack located on the semiconductor substrate. The integrated circuit further includes a transistor embedded in the wiring layer stack. The transistor includes an embedded layer. The embedded layer has a thickness of less than 10 nm. The embedded layer includes at least one two-dimensional crystalline layer including more than 10% metal atoms. Further examples relate to methods for forming integrated circuits.
    Type: Grant
    Filed: December 17, 2018
    Date of Patent: May 25, 2021
    Assignee: Intel Corporation
    Inventors: Carl Naylor, Ashish Agrawal, Kevin Lin, Abhishek Sharma, Mauro Kobrinsky, Christopher Jezewski, Urusa Alaan
  • Publication number: 20210083122
    Abstract: Transistor structures with a channel semiconductor material that is passivated with two-dimensional (2D) crystalline material. The 2D material may comprise a semiconductor having a bandgap offset from a band of the channel semiconductor. The 2D material may be a thin as a few monolayers and have good temperature stability. The 2D material may be a conversion product of a sacrificial precursor material, or of a portion of the channel semiconductor material. The 2D material may comprise one or more metal and a chalcogen. The channel material may be a metal oxide semiconductor suitable for low temperature processing (e.g., IGZO), and the 2D material may also be compatible with low temperature processing (e.g., <450° C.). The 2D material may be a chalcogenide of a metal present in the channel material (e.g., ZnSx or ZnSex) or of a metal absent from the channel material when formed from a sacrificial precursor.
    Type: Application
    Filed: September 13, 2019
    Publication date: March 18, 2021
    Applicant: Intel Corporation
    Inventors: Carl Naylor, Abhishek Sharma, Mauro Kobrinsky, Christopher Jezewski, Urusa Alaan, Justin Weber
  • Publication number: 20200411427
    Abstract: An interconnect structure is disclosed. The interconnect structure includes a first line of interconnects and a second line of interconnects. The first line of interconnects and the second line of interconnects are staggered. The individual interconnects of the second line of interconnects are laterally offset from individual interconnects of the first line of interconnects. A dielectric material is adjacent to at least a portion of the individual interconnects of at least one of the first line of interconnects and the second line of interconnects.
    Type: Application
    Filed: June 27, 2019
    Publication date: December 31, 2020
    Inventors: Kevin Lai LIN, Manish CHANDHOK, Miriam RESHOTKO, Christopher JEZEWSKI, Eungnak HAN, Gurpreet SINGH, Sarah ATANASOV, Ian A. YOUNG
  • Publication number: 20200388685
    Abstract: Transistor structures employing metal chalcogenide channel materials may be formed where a chalcogen is introduced into at least a portion of a precursor material that comprises reactive metal(s). The precursor material may be substantially metallic, or may be a metallic oxide (e.g., an oxide semiconductor). The metal(s) may be transition, Group II, Group III, Group V elements, or alloys thereof. An oxide of one or more such metals (e.g., IGZO) may be converted into a chalcogenide (e.g., IGZSx or IGZSex) having semiconducting properties. The chalcogenide formed in this manner may be only a few monolayers in thickness (and may be more thermally stable than many oxide semiconductors. Where not all of the precursor material is converted, a transistor structure may retain the precursor material, for example as part of a transistor channel or a gate dielectric. Backend transistors including metal chalcogenide channel materials may be fabricated over silicon CMOS circuitry.
    Type: Application
    Filed: June 7, 2019
    Publication date: December 10, 2020
    Applicant: Intel Corporation
    Inventors: Abhishek A. Sharma, Ashish Agarwal, Urusa Alaan, Christopher Jezewski, Kevin Lin, Carl Naylor
  • Publication number: 20200219804
    Abstract: Integrated circuits including selectable vias are disclosed. The techniques are particularly well-suited to back end of line (BEOL) processes. In accordance with some embodiments, a selectable via includes a vertically-oriented thin film transistor structure having a wrap around gate, which can be used to effectively select (or deselect) the selectable via ad hoc. When a selectable via is selected, a signal is allowed to pass through the selectable via. Conversely, when the selectable via is not selected, a signal is not allowed to pass through the selectable via. The selectable characteristic of the selectable via allows multiple vias to share a global interconnect. The global interconnect can be connected to any number of selectable vias, as well as standard vias.
    Type: Application
    Filed: January 9, 2019
    Publication date: July 9, 2020
    Applicant: Intel Corporation
    Inventors: Christopher Jezewski, Ashish Agrawal, Kevin L. Lin, Abhishek Sharma, Carl Naylor, Urusa Alaan
  • Publication number: 20200194338
    Abstract: An example relates to an integrated circuit including a semiconductor substrate, and a wiring layer stack located on the semiconductor substrate. The integrated circuit further includes a transistor embedded in the wiring layer stack. The transistor includes an embedded layer. The embedded layer has a thickness of less than 10 nm. The embedded layer includes at least one two-dimensional crystalline layer including more than 10% metal atoms. Further examples relate to methods for forming integrated circuits.
    Type: Application
    Filed: December 17, 2018
    Publication date: June 18, 2020
    Inventors: Carl NAYLOR, Ashish AGRAWAL, Kevin LIN, Abhishek Sharma, Mauro KOBRINSKY, Christopher JEZEWSKI, Urusa ALAAN
  • Publication number: 20200194376
    Abstract: An aspect of the disclosure relates to an integrated circuit. The integrated circuit includes a first electrically conductive structure, a thin film crystal layer located on the first electrically conductive structure, and a second electrically conductive structure including metal e.g. copper. The second electrically conductive structure is located on the thin film crystal layer. The first electrically conductive structure is electrically connected to the second electrically conductive structure through the thin film crystal layer. The thin film crystal layer may be provided as a copper diffusion barrier.
    Type: Application
    Filed: December 17, 2018
    Publication date: June 18, 2020
    Inventors: Carl NAYLOR, Ashish AGRAWAL, Kevin LIN, Abhishek SHARMA, Mauro KOBRINSKY, Christopher JEZEWSKI, Urusa ALAAN
  • Publication number: 20200185532
    Abstract: A transistor structure includes a layer of active material on a base. The base can be insulator material in some cases. The layer has a channel region between a source region and a drain region. A gate structure is in contact with the channel region and includes a gate electrode and a gate dielectric, where the gate dielectric is between the gate electrode and the active material. An electrical contact is on one or both of the source region and the drain region. The electrical contact has a larger portion in contact with a top surface of the active material and a smaller portion extending through the layer of active material into the base. The active material may be, for example, a transition metal dichalcogenide (TMD) in some embodiments.
    Type: Application
    Filed: December 10, 2018
    Publication date: June 11, 2020
    Applicant: INTEL CORPORATION
    Inventors: Kevin Lin, Abhishek Sharma, Carl Naylor, Urusa Alaan, Christopher Jezewski, Ashish Agrawal
  • Publication number: 20200098874
    Abstract: Embodiments herein describe techniques for an integrated circuit that includes a substrate, a semiconductor device on the substrate, and a contact stack above the substrate and coupled to the semiconductor device. The contact stack includes a contact metal layer, and a semiconducting oxide layer adjacent to the contact metal layer. The semiconducting oxide layer includes a semiconducting oxide material, while the contact metal layer includes a metal with a sufficient Schottky-barrier height to induce an interfacial electric field between the semiconducting oxide layer and the contact metal layer to reject interstitial hydrogen from entering the semiconductor device through the contact stack. Other embodiments may be described and/or claimed.
    Type: Application
    Filed: September 25, 2018
    Publication date: March 26, 2020
    Inventors: Justin WEBER, Harold KENNEL, Abhishek SHARMA, Christopher JEZEWSKI, Matthew V. METZ, Tahir GHANI, Jack T. KAVALIEROS, Benjamin CHU-KUNG, Van H. LE, Arnab SEN GUPTA
  • Publication number: 20200098619
    Abstract: Techniques are disclosed for providing cladded metal interconnects. Given an interconnect trench, a barrier layer is conformally deposited onto the bottom and sidewalls of the trench. A first layer of a bilayer adhesion liner is selectively deposited on the barrier layer, and a second layer of the bilayer adhesion liner is selectively deposited on the first layer. An interconnect metal is deposited into the trench above the bilayer adhesion liner. Any excess interconnect metal is recessed to get the top surface of the interconnect metal to a proper plane. Recessing the excess interconnect metal may include recessing previously deposited excess adhesion liner and barrier layer materials. The exposed top surface of the interconnect metal in the trench is then capped with the bilayer adhesion liner materials to provide a cladded metal interconnect core. In some embodiments, the adhesion liner is a single layer adhesion liner.
    Type: Application
    Filed: September 25, 2018
    Publication date: March 26, 2020
    Applicant: INTEL CORPORATION
    Inventors: Thomas Marieb, Zhiyong Ma, Miriam R. Reshotko, Christopher Jezewski, Flavio Griggio, Rahim Kasim, Nikholas G. Toledo
  • Publication number: 20200006329
    Abstract: Stacked transistor structures having a conductive interconnect between source/drain regions of upper and lower transistors. In some embodiments, the interconnect is provided, at least in part, by highly doped epitaxial material deposited in the upper transistor's source/drain region. In such cases, the epitaxial material seeds off of an exposed portion of semiconductor material of or adjacent to the upper transistor's channel region and extends downward into a recess that exposes the lower transistor's source/drain contact structure. The epitaxial source/drain material directly contacts the lower transistor's source/drain contact structure, to provide the interconnect. In other embodiments, the epitaxial material still seeds off the exposed semiconductor material of or proximate to the channel region and extends downward into the recess, but need not contact the lower contact structure.
    Type: Application
    Filed: June 29, 2018
    Publication date: January 2, 2020
    Applicant: INTEL CORPORATION
    Inventors: AARON D. LILAK, GILBERT DEWEY, CHENG-YING HUANG, CHRISTOPHER JEZEWSKI, EHREN MANNEBACH, RISHABH MEHANDRU, PATRICK MORROW, ANAND S. MURTHY, ANH PHAN, WILLY RACHMADY
  • Patent number: 10201081
    Abstract: A system comprises an article comprising one or more fabric layers, a plurality of electronic devices, each being incorporated into or onto one of the one or more fabric layers, and one or more communication links between two or more of the plurality of electronic devices. Each of the plurality of electronic devices can comprise a flexible substrate coupled to the fabric layer, one or more metallization layers deposited on the flexible substrate, and one or more electronic components electrically coupled to the one or more metallization layers.
    Type: Grant
    Filed: August 14, 2017
    Date of Patent: February 5, 2019
    Assignee: Intel Corporation
    Inventors: Christopher Jezewski, Ravi Pillarisetty, Brian Doyle
  • Publication number: 20170347448
    Abstract: A system comprises an article comprising one or more fabric layers, a. plurality of electronic devices, each being incorporated into or onto one of the one or more fabric layers, and one or more communication links between two or more of the plurality of electronic devices. Each of the plurality of electronic devices can comprise a flexible substrate coupled to the fabric layer, one or more metallization layers deposited on the flexible substrate, and one or more electronic components electrically coupled to the one or more metallization layers.
    Type: Application
    Filed: August 14, 2017
    Publication date: November 30, 2017
    Inventors: Christopher Jezewski, Ravi Pillarisetty, Brian Doyle
  • Patent number: 9736936
    Abstract: A system comprises an article comprising one or more fabric layers, a plurality of electronic devices, each being incorporated into or onto one of the one or more fabric layers, and one or more communication links between two or more of the plurality of electronic devices. Each of the plurality of electronic devices can comprise a flexible substrate coupled to the fabric layer, one or more metallization layers deposited on the flexible substrate, and one or more electronic components electrically coupled to the one or more metallization layers.
    Type: Grant
    Filed: February 1, 2016
    Date of Patent: August 15, 2017
    Assignee: Intel Corporation
    Inventors: Christopher Jezewski, Ravi Pillarisetty, Brian Doyle
  • Publication number: 20160242279
    Abstract: A system comprises an article comprising one or more fabric layers, a plurality of electronic devices, each being incorporated into or onto one of the one or more fabric layers, and one or more communication links between two or more of the plurality of electronic devices. Each of the plurality of electronic devices can comprise a flexible substrate coupled to the fabric layer, one or more metallization layers deposited on the flexible substrate, and one or more electronic components electrically coupled to the one or more metallization layers.
    Type: Application
    Filed: February 1, 2016
    Publication date: August 18, 2016
    Inventors: Christopher Jezewski, Ravi Pillarisetty, Brian Doyle
  • Patent number: 9253884
    Abstract: A system comprises an article comprising one or more fabric layers, a plurality of electronic devices, each being incorporated into or onto one of the one or more fabric layers, and one or more communication links between two or more of the plurality of electronic devices. Each of the plurality of electronic devices can comprise a flexible substrate coupled to the fabric layer, one or more metallization layers deposited on the flexible substrate, and one or more electronic components electrically coupled to the one or more metallization layers.
    Type: Grant
    Filed: December 20, 2013
    Date of Patent: February 2, 2016
    Assignee: Intel Corporation
    Inventors: Christopher Jezewski, Ravi Pillarisetty, Brian Doyle
  • Patent number: 9165824
    Abstract: A metallization layer including a fully clad interconnect and a method of forming a fully clad interconnect. An opening is formed in a dielectric layer, wherein the dielectric layer has a surface and the opening includes walls and a bottom. A diffusion barrier layer and an adhesion layer are deposited on the dielectric layer. An interconnect material is deposited on the dielectric layer and reflowed into the opening forming an interconnect. An adhesion capping layer and diffusion barrier capping layer are deposited over the interconnect. The interconnect is surrounded by the adhesion layer and the adhesion capping layer and the adhesion layer and the adhesion capping layer are surrounded by the diffusion barrier layer and the diffusion capping layer.
    Type: Grant
    Filed: September 27, 2013
    Date of Patent: October 20, 2015
    Assignee: Intel Corporation
    Inventors: Manish Chandhok, Hui Jae Yoo, Christopher Jezewski, Ramanan V. Chebiam, Colin T. Carver
  • Publication number: 20150181692
    Abstract: A system comprises an article comprising one or more fabric layers, a plurality of electronic devices, each being incorporated into or onto one of the one or more fabric layers, and one or more communication links between two or more of the plurality of electronic devices. Each of the plurality of electronic devices can comprise a flexible substrate coupled to the fabric layer, one or more metallization layers deposited on the flexible substrate, and one or more electronic components electrically coupled to the one or more metallization layers.
    Type: Application
    Filed: December 20, 2013
    Publication date: June 25, 2015
    Inventors: Christopher Jezewski, Ravi Pillarisetty, Brian Doyle
  • Publication number: 20150091175
    Abstract: A metallization layer including a fully clad interconnect and a method of forming a fully clad interconnect. An opening is formed in a dielectric layer, wherein the dielectric layer has a surface and the opening includes walls and a bottom. A diffusion barrier layer and an adhesion layer are deposited on the dielectric layer. An interconnect material is deposited on the dielectric layer and reflowed into the opening forming an interconnect. An adhesion capping layer and diffusion barrier capping layer are deposited over the interconnect. The interconnect is surrounded by the adhesion layer and the adhesion capping layer and the adhesion layer and the adhesion capping layer are surrounded by the diffusion barrier layer and the diffusion capping layer.
    Type: Application
    Filed: September 27, 2013
    Publication date: April 2, 2015
    Inventors: MANISH CHANDHOK, HUI JAE YOO, CHRISTOPHER JEZEWSKI, RAMANAN V. CHEBIAM, COLIN T. CARVER
  • Publication number: 20140061918
    Abstract: The present disclosure relates diffusion barrier layers for backend layers for interconnects and their methods of manufacturing. A TaNx/Ta diffusion barrier layer used for backend interconnect is formed at a temperature between about 150-450° C. wherein the Ta film exhibits a body-centered-cubic (BCC) structure and a lower electrical resistivity. Other embodiments are described and claimed.
    Type: Application
    Filed: December 27, 2011
    Publication date: March 6, 2014
    Inventors: Christopher Jezewski, Boyan Boyanov, James J. Clarke, Jacob M. Faber