Abstract: Transistor structures employing metal chalcogenide channel materials may be formed where a chalcogen is introduced into at least a portion of a precursor material that comprises reactive metal(s). The precursor material may be substantially metallic, or may be a metallic oxide (e.g., an oxide semiconductor). The metal(s) may be transition, Group II, Group III, Group V elements, or alloys thereof. An oxide of one or more such metals (e.g., IGZO) may be converted into a chalcogenide (e.g., IGZSx or IGZSex) having semiconducting properties. The chalcogenide formed in this manner may be only a few monolayers in thickness (and may be more thermally stable than many oxide semiconductors. Where not all of the precursor material is converted, a transistor structure may retain the precursor material, for example as part of a transistor channel or a gate dielectric. Backend transistors including metal chalcogenide channel materials may be fabricated over silicon CMOS circuitry.

Abstract: Contacts to p-type source/drain regions comprise a boride, indium, or gallium metal compound layer. The boride, indium, or gallium metal compound layers can aid in forming thermally stable low resistance contacts. A boride, indium, or gallium metal compound layer is positioned between the source/drain region and the contact metal layer. A boride, indium, or gallium metal compound layer can be used in contacts contacting p-type source/drain regions comprising boron, indium, or gallium as the primary dopant, respectively. The boride, indium, or gallium metal compound layers prevent diffusion of boron, indium, or gallium from the source/drain region into the metal contact layer and dopant deactivation in the source/drain region due to annealing and other high-temperature processing steps that occur after contact formation.

Abstract: Contacts to n-type source/drain regions comprise a phosphide or arsenide metal compound layer. The phosphide or arsenide metal compound layers can aid in forming thermally stable low resistance contacts. A phosphide or arsenide metal compound layer is positioned between the source/drain region and the contact metal layer of the contact. A phosphide or arsenic metal compound layer can be used in contacts contacting n-type source/drain regions comprising phosphorous or arsenic as the primary dopant, respectively. The phosphide or arsenide metal compound layers prevent diffusion of phosphorous or arsenic from the source/drain region into the metal contact layer and dopant deactivation in the source/drain region due to annealing and other high-temperature processing steps that occur after contact formation.

Abstract: An example relates to an integrated circuit including a semiconductor substrate, and a wiring layer stack located on the semiconductor substrate. The integrated circuit further includes a transistor embedded in the wiring layer stack. The transistor includes an embedded layer. The embedded layer has a thickness of less than 10 nm. The embedded layer includes at least one two-dimensional crystalline layer including more than 10% metal atoms. Further examples relate to methods for forming integrated circuits.

Abstract: Stacked transistor structures having a conductive interconnect between source/drain regions of upper and lower transistors. In some embodiments, the interconnect is provided, at least in part, by highly doped epitaxial material deposited in the upper transistor’s source/drain region. In such cases, the epitaxial material seeds off of an exposed portion of semiconductor material of or adjacent to the upper transistor’s channel region and extends downward into a recess that exposes the lower transistor’s source/drain contact structure. The epitaxial source/drain material directly contacts the lower transistor’s source/drain contact structure, to provide the interconnect. In other embodiments, the epitaxial material still seeds off the exposed semiconductor material of or proximate to the channel region and extends downward into the recess, but need not contact the lower contact structure.

Abstract: Techniques are disclosed for providing cladded metal interconnects. Given an interconnect trench, a barrier layer is conformally deposited onto the bottom and sidewalls of the trench. A first layer of a bilayer adhesion liner is selectively deposited on the barrier layer, and a second layer of the bilayer adhesion liner is selectively deposited on the first layer. An interconnect metal is deposited into the trench above the bilayer adhesion liner. Any excess interconnect metal is recessed to get the top surface of the interconnect metal to a proper plane. Recessing the excess interconnect metal may include recessing previously deposited excess adhesion liner and barrier layer materials. The exposed top surface of the interconnect metal in the trench is then capped with the bilayer adhesion liner materials to provide a cladded metal interconnect core. In some embodiments, the adhesion liner is a single layer adhesion liner.

Abstract: Stacked transistor structures having a conductive interconnect between source/drain regions of upper and lower transistors. In some embodiments, the interconnect is provided, at least in part, by highly doped epitaxial material deposited in the upper transistor's source/drain region. In such cases, the epitaxial material seeds off of an exposed portion of semiconductor material of or adjacent to the upper transistor's channel region and extends downward into a recess that exposes the lower transistor's source/drain contact structure. The epitaxial source/drain material directly contacts the lower transistor's source/drain contact structure, to provide the interconnect. In other embodiments, the epitaxial material still seeds off the exposed semiconductor material of or proximate to the channel region and extends downward into the recess, but need not contact the lower contact structure.

Abstract: Metallization interconnect structures, integrated circuit devices, and methods related to high aspect ratio interconnects are discussed. A self assembled monolayer is selectively formed on interlayer dielectric sidewalls of an opening that exposes an underlying metallization structure. A first metal is formed on the underlying metallization structure and within only a bottom portion of the self assembled monolayer. The exposed portion of the self assembled monolayer is removed and a second metal is formed over the first metal.

Abstract: Integrated circuit interconnect structures including an interconnect line metallization feature subjected to one or more chalcogenation techniques to form a cap may reduce line resistance. A top portion of a bulk line material may be advantageously crystallized into a metal chalcogenide cap with exceptionally large crystal structure. Accordingly, chalcogenation of a top portion of a bulk material can lower scattering resistance of an interconnect line relative to alternatives where the bulk material is capped with an alternative material, such as an amorphous dielectric or a fine grained metallic or graphitic material.

Abstract: Integrated circuits including selectable vias are disclosed. The techniques are particularly well-suited to back end of line (BEOL) processes. In accordance with some embodiments, a selectable via includes a vertically-oriented thin film transistor structure having a wrap around gate, which can be used to effectively select (or deselect) the selectable via ad hoc. When a selectable via is selected, a signal is allowed to pass through the selectable via. Conversely, when the selectable via is not selected, a signal is not allowed to pass through the selectable via. The selectable characteristic of the selectable via allows multiple vias to share a global interconnect. The global interconnect can be connected to any number of selectable vias, as well as standard vias.

Abstract: An interconnect structure is disclosed. The interconnect structure includes a first line of interconnects and a second line of interconnects. The first line of interconnects and the second line of interconnects are staggered. The individual interconnects of the second line of interconnects are laterally offset from individual interconnects of the first line of interconnects. A dielectric material is adjacent to at least a portion of the individual interconnects of at least one of the first line of interconnects and the second line of interconnects.

Abstract: Embodiments herein describe techniques for an integrated circuit that includes a substrate, a semiconductor device on the substrate, and a contact stack above the substrate and coupled to the semiconductor device. The contact stack includes a contact metal layer, and a semiconducting oxide layer adjacent to the contact metal layer. The semiconducting oxide layer includes a semiconducting oxide material, while the contact metal layer includes a metal with a sufficient Schottky-barrier height to induce an interfacial electric field between the semiconducting oxide layer and the contact metal layer to reject interstitial hydrogen from entering the semiconductor device through the contact stack. Other embodiments may be described and/or claimed.

Abstract: Integrated circuitry interconnect structures comprising a first metal and a graphene cap over a top surface of the first metal. Within the interconnect structure an amount of a second metal, nitrogen, or silicon is greater proximal to an interface of the graphene cap. The presence of the second metal, nitrogen, or silicon may improve adhesion of the graphene to the first metal and/or otherwise improve electromigration resistance of a graphene capped interconnect structure. The second metal, nitrogen, or silicon may be introduced into the first metal during deposition of the first metal, or during a post-deposition treatment of the first metal. The second metal, nitrogen, or silicon may be introduced prior to, or after, capping the first metal with graphene.

Abstract: IC interconnect structures including subtractively patterned features. Feature ends may be defined through multiple patterning of multiple cap materials for reduced misregistration. Subtractively patterned features may be lines integrated with damascene vias or with subtractively patterned vias, or may be vias integrated with damascene lines or with subtractively patterned lines. Subtractively patterned vias may be deposited as part of a planar metal layer and defined currently with interconnect lines. Subtractively patterned features may be integrated with air gap isolation structures. Subtractively patterned features may be include a barrier material on the bottom, top, or sidewall. A bottom barrier of a subtractively patterned features may be deposited with an area selective technique to be absent from an underlying interconnect feature. A barrier of a subtractively patterned feature may comprise graphene or a chalcogenide of a metal in the feature or in a seed layer.

Abstract: A transistor structure includes a layer of active material on a base. The base can be insulator material in some cases. The layer has a channel region between a source region and a drain region. A gate structure is in contact with the channel region and includes a gate electrode and a gate dielectric, where the gate dielectric is between the gate electrode and the active material. An electrical contact is on one or both of the source region and the drain region. The electrical contact has a larger portion in contact with a top surface of the active material and a smaller portion extending through the layer of active material into the base. The active material may be, for example, a transition metal dichalcogenide (TMD) in some embodiments.

Abstract: IC interconnect structures including subtractively patterned features. Feature ends may be defined through multiple patterning of multiple cap materials for reduced misregistration. Subtractively patterned features may be lines integrated with damascene vias or with subtractively patterned vias, or may be vias integrated with damascene lines or with subtractively patterned lines. Subtractively patterned vias may be deposited as part of a planar metal layer and defined currently with interconnect lines. Subtractively patterned features may be integrated with air gap isolation structures. Subtractively patterned features may be include a barrier material on the bottom, top, or sidewall. A bottom barrier of a subtractively patterned features may be deposited with an area selective technique to be absent from an underlying interconnect feature. A barrier of a subtractively patterned feature may comprise graphene or a chalcogenide of a metal in the feature or in a seed layer.

Abstract: An aspect of the disclosure relates to an integrated circuit. The integrated circuit includes a first electrically conductive structure, a thin film crystal layer located on the first electrically conductive structure, and a second electrically conductive structure including metal e.g. copper. The second electrically conductive structure is located on the thin film crystal layer. The first electrically conductive structure is electrically connected to the second electrically conductive structure through the thin film crystal layer. The thin film crystal layer may be provided as a copper diffusion barrier.

Abstract: IC interconnect structures including subtractively patterned features. Feature ends may be defined through multiple patterning of multiple cap materials for reduced misregistration. Subtractively patterned features may be lines integrated with damascene vias or with subtractively patterned vias, or may be vias integrated with damascene lines or with subtractively patterned lines. Subtractively patterned vias may be deposited as part of a planar metal layer and defined currently with interconnect lines. Subtractively patterned features may be integrated with air gap isolation structures. Subtractively patterned features may be include a barrier material on the bottom, top, or sidewall. A bottom barrier of a subtractively patterned features may be deposited with an area selective technique to be absent from an underlying interconnect feature. A barrier of a subtractively patterned feature may comprise graphene or a chalcogenide of a metal in the feature or in a seed layer.

Abstract: Integrated circuit interconnect structures including an interconnect metallization feature with a barrier material comprising a metal and a chalcogen. Introduction of the chalcogen may improve diffusion barrier properties at a given barrier material layer thickness with increasing the barrier layer thickness. A barrier material, such as TaN, may be deposited at minimal thickness, and doped with a chalcogen before or after one or more fill materials are deposited over the barrier material. During thermal processing mobile chalcogen impurities may collect within regions within the barrier material to high enough concentrations for at least a portion of the barrier material to be converted into a metal chalcogenide layer. The metal chalcogenide layer may have greater crystallinity than a remainder of the barrier layer.

Abstract: Integrated circuit interconnect structures including a metallization line with a bottom barrier material, and a metallization via lacking a bottom barrier material. Barrier material at a bottom of the metallization line may, along with barrier material on a sidewall of the metallization line, mitigate the diffusion or migration of fill metal from the line. An absence of barrier material at a bottom of the via may reduce via resistance and/or facilitate the use of a highly resistive barrier material that may enhance the scalability of interconnect structures. A number of masking materials and patterning techniques may be integrated into a dual damascene interconnect process to provide for both a barrier material and a low resistance via unburden by the barrier material.