Abstract: Embodiments of the present invention provide apparatus for automatic valuation of articles. The apparatus may comprise an article receiving device arranged to receive an article therein; and an article assessment device arranged to determine the presence of a prescribed one or more materials in said article along with the quantity thereof, the article assessment device being arranged to determine a value of the one or more materials present in the article based on a stored amount of the value of a given quantity of each of said one or more materials, and the quantity of the one or more materials present in the article as determined by the article assessment device, and to output to the user the value of said article based on the value of the one or more materials and/or output to the user the value of the one or more materials.

Abstract: A method for reducing computational steps in a digital processor including multiplications producing a plurality of multiplication products. This method specifies a desired multiplication function to be implemented in a digital processor, the desired multiplication function having a respective set of initial coefficients corresponding to each digital multiplier stage of the multiplication function. An initial total number of non-zero bits of the initial coefficients is determined and the initial coefficients are modified. Further, a resulting number of non-zero bits in the modified set of coefficients is quantified. Finally, the modified set of coefficients that result in a reduced number of non-zero bits as compared to the initial coefficients is chosen. The new modified coefficients are implemented in the device by constructing the digital multiplier stages with the modified coefficients.

Abstract: A method for reducing computational steps in a digital processor including multiplications producing a plurality of multiplication products. This method specifies a desired multiplication function to be implemented in a digital processor, the desired multiplication function having a respective set of initial coefficients corresponding to each digital multiplier stage of the multiplication function. An initial total number of non-zero bits of the initial coefficients is determined and the initial coefficients are modified. Further, a resulting number of non-zero bits in the modified set of coefficients is quantified. Finally, the modified set of coefficients that result in a reduced number of non-zero bits as compared to the initial coefficients is chosen. The new modified coefficients are implemented in the device by constructing the digital multiplier stages with the modified coefficients.

Abstract: An arbitration and synchronization method and system for allowing multiple processors to access a shared memory includes an arbitrator. The arbitrator is operable with the processors for enabling each of the processors exclusive access to the memory for a predetermined time period on a rotating basis. In operation, a time period of a time frame is associated with each of the processors. The time periods of the time frame are then counted. The arbitrator then enables a processor to have exclusive access to the shared memory for the time period associated with the processor when the counted time period is the time period associated with the processor.

Abstract: A digital signal processing architecture for an audio system combines multiple functions in programmable and reconfigurable blocks to achieve an efficient use of hardware and chip area. AM, FM, and audio functions can be performed using the same reconfigurable hardware while taking into account the different sample rates and processing functions required for each.

Abstract: A carrier-based signal is received from a tuner and is digitized to produce a digital intermediate frequency (IF) signal. Automatic gain control is applied to the carrier-based signal either prior to or after digitization. An adaptive intermediate frequency bandwidth control system detects IF signal level after channel filtering. The level is compared to a predetermined threshold having a value related to the known signal level of the AGC'ed signal which is being input to the channel filter in order to provide a measure of either 1) the presence of interfering adjacent channels, or 2) reception or a weak signal which can't be compensated for by AGC. The IF bandwidth is narrowed in either circumstance. Digital FIR or IIR filtering is used. The invention allows bandwidth switching to be done very quickly with minimal transient effects. A threshold value is selected depending upon the IF channel bandwidth being used at any given time.

Abstract: An adaptive intermediate frequency bandwidth control system detects IF signal levels both before and after channel filtering. The two levels are compared to provide a measure of the presence of interfering adjacent channels. This measure is compared to a programmable threshold and the IF bandwidth is narrowed if any interferers are detected. Digital FIR or IIR filtering is used. The invention allows bandwidth switching to be done very quickly with minimal transient effects. A difference threshold is selected depending upon the IF channel bandwidth being used at any given time.