Abstract: The present disclosure relates to systems, methods, and computer readable media for modeling thermal effects within a multi-laser device. For example, systems described herein may include a plurality of laser devices that output energy streams having corresponding operating windows. One or more systems described herein may include a set of accumulators for tracking quantities of energy samples within operating windows and populating a queue representative of the tracked quantities. One or more systems described herein may additionally include filters and a summing module for determining temperature values for operating windows and synchronizing the temperature values with one another to determine an accurate system temperature for the multi-laser device. The features described herein facilitate synchronization of data for corresponding operating windows to provide an accurate determination of system temperature based on a combination of self-heating and crosstalk effects between multiple laser devices.

Abstract: The present disclosure relates to systems, methods, and computer readable media for modeling thermal effects within a multi-laser device. For example, systems described herein may include a plurality of laser devices that output energy streams having corresponding operating windows. One or more systems described herein may include a set of accumulators for tracking quantities of energy samples within operating windows and populating a queue representative of the tracked quantities. One or more systems described herein may additionally include filters and a summing module for determining temperature values for operating windows and synchronizing the temperature values with one another to determine an accurate system temperature for the multi-laser device. The features described herein facilitate synchronization of data for corresponding operating windows to provide an accurate determination of system temperature based on a combination of self-heating and crosstalk effects between multiple laser devices.

Abstract: The present disclosure relates to systems, methods, and computer readable media for modeling thermal effects within a multi-laser device. For example, systems described herein may include a plurality of laser devices that output energy streams having corresponding operating windows. One or more systems described herein may include a set of accumulators for tracking quantities of energy samples within operating windows and populating a queue representative of the tracked quantities. One or more systems described herein may additionally include filters and a summing module for determining temperature values for operating windows and synchronizing the temperature values with one another to determine an accurate system temperature for the multi-laser device. The features described herein facilitate synchronization of data for corresponding operating windows to provide an accurate determination of system temperature based on a combination of self-heating and crosstalk effects between multiple laser devices.

Abstract: Systems and methods are disclosed herein for providing improved cache structures and methods that are optimally sized to support a predetermined range of late stage adjustments and in which image data is intelligently read out of DRAM and cached in such a way as to eliminate re-fetching of input image data from DRAM and minimize DRAM bandwidth and power. The systems and methods can also be adapted to work with compressed image data and multiple LSR processing engines.

Abstract: Techniques for post-rendering image transformation including outputting an image frame including a plurality of first pixels by sequentially generating and outputting multiple color component fields including a first color component field and a second color component field by applying one or more two-dimensional (2D) image transformations to at least one portion of the plurality of source pixels by first, second, and third image transformation pipelines, to generate transformed pixel color data for the first color component field and the second color component field.

Abstract: Systems and methods are disclosed herein for providing improved cache structures and methods that are optimally sized to support a predetermined range of late stage adjustments and in which image data is intelligently read out of DRAM and cached in such a way as to eliminate re-fetching of input image data from DRAM and minimize DRAM bandwidth and power. The systems and methods can also be adapted to work with compressed image data and multiple LSR processing engines.

Abstract: Systems and methods are disclosed herein for providing improved cache structures and methods that are optimally sized to support a predetermined range of late stage adjustments and in which image data is intelligently read out of DRAM and cached in such a way as to eliminate re-fetching of input image data from DRAM and minimize DRAM bandwidth and power. The systems and methods can also be adapted to work with compressed image data and multiple LSR processing engines.

Abstract: Systems and methods are disclosed herein for providing improved cache structures and methods that are optimally sized to support a predetermined range of late stage adjustments and in which image data is intelligently read out of DRAM and cached in such a way as to eliminate re-fetching of input image data from DRAM and minimize DRAM bandwidth and power. The systems and methods can also be adapted to work with compressed image data.

Abstract: Systems and methods are disclosed herein for providing improved cache structures and methods that are optimally sized to support a predetermined range of late stage adjustments and in which image data is intelligently read out of DRAM and cached in such a way as to eliminate re-fetching of input image data from DRAM and minimize DRAM bandwidth and power.

Abstract: Techniques for post-rendering image transformation including outputting an image frame including a plurality of first pixels by sequentially generating and outputting multiple color component fields including a first color component field and a second color component field by applying one or more two-dimensional (2D) image transformations to at least one portion of the plurality of source pixels by first, second, and third image transformation pipelines, to generate transformed pixel color data for the first color component field and the second color component field.

Abstract: Systems and methods are disclosed herein for providing improved cache structures and methods that are optimally sized to support a predetermined range of late stage adjustments and in which image data is intelligently read out of DRAM and cached in such a way as to eliminate re-fetching of input image data from DRAM and minimize DRAM bandwidth and power. The systems and methods can also be adapted to work with compressed image data and multiple LSR processing engines.

Abstract: Systems and methods are disclosed herein for providing improved cache structures and methods that are optimally sized to support a predetermined range of late stage adjustments and in which image data is intelligently read out of DRAM and cached in such a way as to eliminate re-fetching of input image data from DRAM and minimize DRAM bandwidth and power. The systems and methods can also be adapted to work with compressed image data.

Abstract: Systems and methods are disclosed herein for providing improved cache structures and methods that are optimally sized to support a predetermined range of late stage adjustments and in which image data is intelligently read out of DRAM and cached in such a way as to eliminate re-fetching of input image data from DRAM and minimize DRAM bandwidth and power.

Abstract: Systems and methods are disclosed herein for providing improved cache structures and methods that are optimally sized to support a predetermined range of late stage adjustments and in which image data is intelligently read out of DRAM and cached in such a way as to eliminate re-fetching of input image data from DRAM and minimize DRAM bandwidth and power. The systems and methods can also be adapted to work with compressed image data.

Abstract: A method and apparatus are provided for implementing multiple configurable sub-busses of a point-to-point bus. Each of a plurality of bus interconnects include a transmit interface and a receive interface connected to the point-to-point bus. Each transmit interface includes a transmit buffer and a serializer coupled between the buffer and the point-to-point bus. The transmit buffer provides an asynchronous interface between a transmit source and the serializer. The serializer receives data and control signals from the transmit buffer at a first frequency and transmits data and control signals over the point-to-point bus at a higher second frequency. Transmit steering logic is coupled between the transmit source and each transmit buffer of the plurality of bus interconnects. Transmit steering logic directs data and control signals from transmit source to each selected one of the transmit buffers based upon a selected bus configuration.

Abstract: A method and apparatus are provided for implementing chip-to-chip interconnect bus initialization. The chip-to-chip interconnect bus includes first and second unidirectional buses for full duplex communications between two chips. A lower than normal bus frequency is used during the initialization process. A transmit initialization sequencer of a source transmits predefined SYNC symbols on the connected unidirectional bus. A receive initialization sequencer of a destination chip checks for a defined number of valid SYNC or IDLE symbols. When the receive initialization sequencer of a destination detects the defined number of valid SYNC or IDLE symbols, the receive initialization sequencer triggers a transmit initialization sequencer of the destination to transmit IDLE symbols on the connected unidirectional bus. The transmitted IDLE symbols are detected by a receive initialization sequencer at the source, indicating that both ends of the interconnect bus have synchronized.

Abstract: A method and apparatus are provided for implementing multiple configurable sub-busses of a point-to-point bus. Each of a plurality of bus interconnects include a transmit interface and a receive interface connected to the point-to-point bus. Each transmit interface includes a transmit buffer and a serializer coupled between the buffer and the point-to-point bus. The transmit buffer provides an asynchronous interface between a transmit source and the serializer. The serializer receives data and control signals from the transmit buffer at a first frequency and transmits data and control signals over the point-to-point bus at a higher second frequency. Transmit steering logic is coupled between the transmit source and each transmit buffer of the plurality of bus interconnects. Transmit steering logic directs data and control signals from transmit source to each selected one of the transmit buffers based upon a selected bus configuration.

Abstract: A method and apparatus are provided for implementing chip-to-chip interconnect bus initialization. The chip-to-chip interconnect bus includes first and second unidirectional buses for full duplex communications between two chips. A lower than normal bus frequency is used during the initialization process. A transmit initialization sequencer of a source transmits predefined SYNC symbols on the connected unidirectional bus. A receive initialization sequencer of a destination chip checks for a defined number of valid SYNC or IDLE symbols. When the receive initialization sequencer of a destination detects the defined number of valid SYNC or IDLE symbols, the receive initialization sequencer triggers a transmit initialization sequencer of the destination to transmit IDLE symbols on the connected unidirectional bus. The transmitted IDLE symbols are detected by a receive initialization sequencer at the source, indicating that both ends of the interconnect bus have synchronized.