Abstract: Methods, systems, and devices supporting an interface for refreshing non-volatile memory are described. In some examples, a host system may communicate with a memory system, where both the host system and the memory system may be included within a vehicle (e.g., an automotive system). The host system may receive an indication that the vehicle is powering down (e.g., shutting off an engine or lowering power output from a battery). The host system may switch from a first mode corresponding to a first power usage to a second mode corresponding to a second, lower power usage in response to the vehicle powering down, the second mode supporting initiation of a refresh operation at the memory device. The host system may transmit a refresh command to the memory system to refresh non-volatile memory while the vehicle is powered down if the host system is operating in the second mode of operation.

Abstract: Methods, systems, and devices for triggering a refresh for non-volatile memory are described. A host system may communicate with a memory system, where the host system and memory system may be included within a vehicle (e.g., an automotive system). The host system may receive an indication that the vehicle is powering down and may enter a power off state in response to the indication. The host system may detect a trigger (e.g., using a time or temperature input) to switch back to a power on state while the vehicle is powered down, the trigger associated with performing a refresh operation at the memory system. The host system may enter the power on state and may transmit a power on command to the memory system. The memory system may perform the refresh operation on one or more memory cells while the vehicle remains in the powered down state.

Abstract: A solid state drive having at least one component solid state drive, a spare solid state drive, and a drive aggregator. The drive aggregator has at least one host interface, at least one drive interface connected to the at least one component solid state drive, and an interface connected to the spare solid state drive. The drive aggregator is configured to maintain, in the spare solid state drive, a copy of a dataset that is stored in the component solid state drive. In response to a failure of the component solid state drive, the drive aggregator is configured to substitute a function of the component solid state drive with respect to the dataset with a corresponding function of the spare solid state drive, based on the copy of the dataset maintained in the spare solid state drive.

Abstract: Systems, methods and apparatuses of processing overwhelming stimuli in vehicle data recorders. For example, a data recorder can have resources, such as memory components, a controller, an inference engine, etc. The resources can be partitioned into a first subset and a second subset. Abnormal stimuli in an input stream to the recorder may cause delay for real time processing. In response, a time sliced segment of the input stream is selected and assigned to the first subset; and a remaining segment is assigned to the second subset. The first and second subsets can separately process the time sliced segment and the remaining segment in parallel and thus avoid delay in the processing of the remaining segment. An artificial neural network (ANN) can determine a width for selecting the segment processed by the first subset; and the processing result can include a preferred width used to train the ANN.

Abstract: A solid state drive having a drive aggregator and a plurality of component solid state drive, including a first component solid state drive and a second component solid state drive. The drive aggregator has at least one host interface, and a plurality of drive interfaces connected to the plurality of component solid state drives. The drive aggregator is configured to generate, in the second solid state drive, a copy of a dataset that is stored in the first component solid state drive. In response to a failure of the first component solid state drive, the drive aggregator is configured to substitute a function of the first component solid state drive with respect to the dataset with a corresponding function of the second component solid state drive, based on the copy of the dataset generated in the second component solid state drive.

Abstract: A solid state drive having a drive aggregator and multiple component solid state drives. The drive aggregator associates the host interfaces with different logical address spaces, interprets commands received from the host interfaces in the different logical address spaces, and implements the commands using the plurality of component solid state drives. Some of the host interfaces can be configured to share a common logical address space. Some of the logical address spaces can be configured to have an overlapping region that are hosted on the same set of memory units such that the memory units can be addressed in any of the logical address spaces having the overlapping region.

Abstract: Systems, methods, and apparatus related to memory devices such as solid state drives. In one approach, data is received from a host system (e.g., data to be written to an SSD). The received data is encoded using a first error correction code to generate first parity data. A temperature at which memory cells of a storage device (e.g., the SSD) will store the received data is determined. In response to determining the temperature, a first portion of the received data is identified (e.g., data in memory storage that is error-prone at a predicted higher temperature that has been determined based on output from an artificial neural network using sensor(s) input). The identified first portion is encoded using a second error correction code to generate second parity data. The second error correction code has a higher error correction capability than the first error correction code. The encoded first portion, the first parity data, and the second parity data are stored in the memory cells of the storage device.

Abstract: A solid state drive having a drive aggregator and a plurality of component solid state drives. The drive aggregator is configured to map logical addresses identified in one or more first commands into multiple logical address groups defined respectively in multiple component solid state drives. According to the one or more first commands and the logical address mapping, the drive aggregator generates multiple second commands and transmits the multiple second commands in parallel to the multiple component solid state drives to perform an operation identified by the one or more first commands.

Abstract: Systems, methods, and apparatus related to memory devices such as solid state drives. In one approach, data is received from a host system (e.g., data to be written to an SSD). The received data is encoded using a first error correction code to generate first parity data. A temperature at which memory cells of a storage device (e.g., the SSD) will store the received data is determined. In response to determining the temperature, a first portion of the received data is identified (e.g., data in memory storage that is error-prone at a predicted higher temperature that has been determined based on output from an artificial neural network using sensor(s) input). The identified first portion is encoded using a second error correction code to generate second parity data. The second error correction code has a higher error correction capability than the first error correction code. The encoded first portion, the first parity data, and the second parity data are stored in the memory cells of the storage device.

Abstract: Systems, methods, and apparatus related to memory devices such as solid state drives. In one approach, data is received from a host system (e.g., data to be written to an SSD). The received data is encoded using a first error correction code to generate first parity data. A temperature at which memory cells of a storage device (e.g., the SSD) will store the received data is determined. In response to determining the temperature, a first portion of the received data is identified (e.g., data in memory storage that is error-prone at a predicted higher temperature that has been determined based on output from an artificial neural network using sensor(s) input). The identified first portion is encoded using a second error correction code to generate second parity data. The second error correction code has a higher error correction capability than the first error correction code. The encoded first portion, the first parity data, and the second parity data are stored in the memory cells of the storage device.

Abstract: Systems, methods and apparatuses of processing overwhelming stimuli in vehicle data recorders. For example, a data recorder can have resources, such as memory components, a controller, an inference engine, etc. The resources can be partitioned into a first subset and a second subset. Abnormal stimuli in an input stream to the recorder may cause delay for real time processing. In response, a time sliced segment of the input stream is selected and assigned to the first subset; and a remaining segment is assigned to the second subset. The first and second subsets can separately process the time sliced segment and the remaining segment in parallel and thus avoid delay in the processing of the remaining segment. An artificial neural network (ANN) can determine a width for selecting the segment processed by the first subset; and the processing result can include a preferred width used to train the ANN.

Abstract: A solid state drive having a drive aggregator and multiple component solid state drives. Different component solid state drives in solid state drive are configured with different optimizations of memory/storage operations. An address map in the solid state drive is used by the drive aggregator to host different namespaces in the component solid state drives based on optimization requirements of the namespaces and based on the optimizations of memory operations that have been implement in the component solid state drives.

Abstract: A solid state drive having a drive aggregator and multiple component solid state drives. Different component solid state drives in solid state drive are configured with different optimizations of memory/storage operations. An address map in the solid state drive is used by the drive aggregator to host different namespaces in the component solid state drives based on optimization requirements of the namespaces and based on the optimizations of memory operations that have been implement in the component solid state drives.

Abstract: A solid state drive having a drive aggregator and a plurality of component solid state drives. The drive aggregator is configured to map logical addresses identified in one or more first commands into multiple logical address groups defined respectively in multiple component solid state drives. According to the one or more first commands and the logical address mapping, the drive aggregator generates multiple second commands and transmits the multiple second commands in parallel to the multiple component solid state drives to perform an operation identified by the one or more first commands.

Abstract: A solid state drive having a drive aggregator and multiple component solid state drives. The drive aggregator associates the host interfaces with different logical address spaces, interprets commands received from the host interfaces in the different logical address spaces, and implements the commands using the plurality of component solid state drives. Some of the host interfaces can be configured to share a common logical address space. Some of the logical address spaces can be configured to have an overlapping region that are hosted on the same set of memory units such that the memory units can be addressed in any of the logical address spaces having the overlapping region.

Abstract: A solid state drive having a drive aggregator and a plurality of component solid state drives. The drive aggregator is configured to map logical addresses identified in one or more first commands into multiple logical address groups defined respectively in multiple component solid state drives. According to the one or more first commands and the logical address mapping, the drive aggregator generates multiple second commands and transmits the multiple second commands in parallel to the multiple component solid state drives to perform an operation identified by the one or more first commands.

Abstract: A solid state drive having a drive aggregator and multiple component solid state drives. The drive aggregator associates the host interfaces with different logical address spaces, interprets commands received from the host interfaces in the different logical address spaces, and implements the commands using the plurality of component solid state drives. Some of the host interfaces can be configured to share a common logical address space. Some of the logical address spaces can be configured to have an overlapping region that are hosted on the same set of memory units such that the memory units can be addressed in any of the logical address spaces having the overlapping region.

Abstract: A solid state drive having a drive aggregator and a plurality of component solid state drives. The drive aggregator is configured to map logical addresses identified in one or more first commands into multiple logical address groups defined respectively in multiple component solid state drives. According to the one or more first commands and the logical address mapping, the drive aggregator generates multiple second commands and transmits the multiple second commands in parallel to the multiple component solid state drives to perform an operation identified by the one or more first commands.

Abstract: A solid state drive having a drive aggregator and a plurality of component solid state drive, including a first component solid state drive and a second component solid state drive. The drive aggregator has at least one host interface, and a plurality of drive interfaces connected to the plurality of component solid state drives. The drive aggregator is configured to generate, in the second solid state drive, a copy of a dataset that is stored in the first component solid state drive. In response to a failure of the first component solid state drive, the drive aggregator is configured to substitute a function of the first component solid state drive with respect to the dataset with a corresponding function of the second component solid state drive, based on the copy of the dataset generated in the second component solid state drive.

Abstract: A solid state drive having a drive aggregator and multiple component solid state drives. Different component solid state drives in solid state drive are configured with different optimizations of memory/storage operations. An address map in the solid state drive is used by the drive aggregator to host different namespaces in the component solid state drives based on optimization requirements of the namespaces and based on the optimizations of memory operations that have been implement in the component solid state drives.