Patents by Inventor Christopher Joseph Curl

Christopher Joseph Curl has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11017850
    Abstract: Method and apparatus for managing data in a non-volatile memory (NVM) of a storage device, such as a solid-state drive (SSD). In some embodiments, first data are read from the NVM using an initial set of read voltages over a selected range of cross-temperature differential (CTD) values comprising a difference between a programming temperature at which the first data are programmed to the NVM cells and a reading temperature at which the first data are subsequently read from the NVM cells. A master set of read voltages is thereafter selected that provides a lowest acceptable error rate performance level over the entirety of the CTD range, and the master set of read voltages is thereafter used irrespective of NVM temperature. In some cases, the master set of read voltages may be further adjusted for different word line addresses, program/erase counts, read counts, data aging, etc.
    Type: Grant
    Filed: August 22, 2019
    Date of Patent: May 25, 2021
    Assignee: Seagate Technology LLC
    Inventors: Kurt Walter Getreuer, Darshana H. Mehta, Antoine Khoueir, Christopher Joseph Curl
  • Patent number: 11017864
    Abstract: Method and apparatus for managing data in a non-volatile memory (NVM) of a storage device, such as a solid-state drive (SSD). An initial temperature is stored associated with the programming of data to memory cells in the NVM. A current temperature associated with the NVM is subsequently measured. At such time that a difference interval between the initial and current temperatures exceeds a selected threshold, a preemptive parametric adjustment operation is applied to the NVM. The operation may include a read voltage calibration, a read voltage increment adjustment, and/or a forced garbage collection operation. The operation results in a new set of read voltage set points for the data suitable for the current temperature, and is carried out independently of any pending read commands associated with the data. The initial temperature can be measured during the programming of the data, or measured during the most recent read voltage calibration operation.
    Type: Grant
    Filed: June 26, 2019
    Date of Patent: May 25, 2021
    Assignee: Seagate Technology LLC
    Inventors: Kurt Walter Getreuer, Darshana H. Mehta, Antoine Khoueir, Christopher Joseph Curl
  • Patent number: 10956064
    Abstract: Method and apparatus for managing data in a non-volatile memory (NVM) of a storage device, such as a solid-state drive (SSD). A circuit measures programming and reading temperatures for a set of memory cells in the NVM. Error rates are determined for each of the reading operations carried out upon the data stored in the memory cells. A code rate for the NVM is adjusted to maintain a selected error rate for the memory cells. The code rate is adjusted in relation to a cross-temperature differential (CTD) value exceeding a selected threshold. The code rate can include an inner code rate as a ratio of user data bits to the total number of user data bits and error correction code (ECC) bits in each code word written to the NVM, and/or an outer code rate as a strength or size of a parity value used to protect multiple code words.
    Type: Grant
    Filed: June 28, 2019
    Date of Patent: March 23, 2021
    Assignee: Seagate Technology LLC
    Inventors: Darshana H. Mehta, Kurt Walter Getreuer, Antoine Khoueir, Christopher Joseph Curl
  • Publication number: 20210057024
    Abstract: Method and apparatus for managing data in a non-volatile memory (NVM) of a storage device, such as a solid-state drive (SSD). In some embodiments, first data are read from the NVM using an initial set of read voltages over a selected range of cross-temperature differential (CTD) values comprising a difference between a programming temperature at which the first data are programmed to the NVM cells and a reading temperature at which the first data are subsequently read from the NVM cells. A master set of read voltages is thereafter selected that provides a lowest acceptable error rate performance level over the entirety of the CTD range, and the master set of read voltages is thereafter used irrespective of NVM temperature. In some cases, the master set of read voltages may be further adjusted for different word line addresses, program/erase counts, read counts, data aging, etc.
    Type: Application
    Filed: August 22, 2019
    Publication date: February 25, 2021
    Inventors: Kurt Walter Getreuer, Darshana H. Mehta, Antoine Khoueir, Christopher Joseph Curl
  • Publication number: 20200411110
    Abstract: Method and apparatus for managing data in a non-volatile memory (NVM) of a storage device, such as a solid-state drive (SSD). An initial temperature is stored associated with the programming of data to memory cells in the NVM. A current temperature associated with the NVM is subsequently measured. At such time that a difference interval between the initial and current temperatures exceeds a selected threshold, a preemptive parametric adjustment operation is applied to the NVM. The operation may include a read voltage calibration, a read voltage increment adjustment, and/or a forced garbage collection operation. The operation results in a new set of read voltage set points for the data suitable for the current temperature, and is carried out independently of any pending read commands associated with the data. The initial temperature can be measured during the programming of the data, or measured during the most recent read voltage calibration operation.
    Type: Application
    Filed: June 26, 2019
    Publication date: December 31, 2020
    Inventors: Kurt Walter Getreuer, Darshana H. Mehta, Antoine Khoueir, Christopher Joseph Curl
  • Publication number: 20200409579
    Abstract: Method and apparatus for managing data in a non-volatile memory (NVM) of a storage device, such as a solid-state drive (SSD). A circuit measures programming and reading temperatures for a set of memory cells in the NVM. Error rates are determined for each of the reading operations carried out upon the data stored in the memory cells. A code rate for the NVM is adjusted to maintain a selected error rate for the memory cells. The code rate is adjusted in relation to a cross-temperature differential (CTD) value exceeding a selected threshold. The code rate can include an inner code rate as a ratio of user data bits to the total number of user data bits and error correction code (ECC) bits in each code word written to the NVM, and/or an outer code rate as a strength or size of a parity value used to protect multiple code words.
    Type: Application
    Filed: June 28, 2019
    Publication date: December 31, 2020
    Inventors: Darshana H. Mehta, Kurt Walter Getreuer, Antoine Khoueir, Christopher Joseph Curl