Abstract: A system for performing diffraction analysis, includes a mill for removing a surface portion of a sample, and an analyzer for performing diffraction analysis on the milled sample.

Abstract: A system for performing diffraction analysis, includes a mill for removing a surface portion of a sample, and an analyzer for performing diffraction analysis on the milled sample.

Abstract: A system for performing diffraction analysis, includes a focused ion beam (FIB) device for preparing a sample, a mill for removing a surface portion of the prepared sample, and an analyzer for performing diffraction analysis on the milled sample.

Abstract: A system for performing diffraction analysis, includes a focused ion beam (FIB) device for preparing a sample, a mill for removing a surface portion of the prepared sample, and an analyzer for performing diffraction analysis on the milled sample.

Abstract: A system for performing nano beam diffraction (NBD) analysis, includes a focused ion beam (FIB) device for preparing a transmission electron microscopy (TEM) sample, a broad beam ion mill for milling the TEM sample to remove a surface portion of the TEM sample, and a strain analyzer for performing NBD analysis on the milled TEM sample to acquire diffraction data.

Abstract: A system for performing nano beam diffraction (NBD) analysis, includes a focused ion beam (FIB) device for preparing a transmission electron microscopy (TEM) sample, a broad beam ion mill for milling the TEM sample to remove a surface portion of the TEM sample, and a strain analyzer for performing NBD analysis on the milled TEM sample to acquire diffraction data.

Abstract: As disclosed herein, a method is provided for simultaneously patterning features having a first width in a first portion such as a logic portion of an integrated circuit, and having a second width in a second portion such as an array portion of an integrated circuit. The method includes depositing a feature layer over a substrate and a hardmask material layer thereover. Photoresist patterns are then formed in the first and second portions with a critical dimension mask, and are then used to etch the hardmask material layer into hardmask patterns. Sidewall spacers are provided on sidewalls of the hardmask patterns in the second portion. Then, the feature layer is simultaneously etched in both first and second portions, using the hardmask patterns in the first portion to define features having a first width, and using the hardmask patterns and the sidewall spacers in the second portion to define features having a second width.

Abstract: As disclosed herein, a method is provided for simultaneously patterning features having a first width in a first portion such as a logic portion of an integrated circuit, and having a second width in a second portion such as an array portion of an integrated circuit. The method includes depositing a feature layer over a substrate and a hardmask material layer thereover. Photoresist patterns are then formed in the first and second portions with a critical dimension mask, and are then used to etch the hardmask material layer into hardmask patterns. Sidewall spacers are provided on sidewalls of the hardmask patterns in the second portion. Then, the feature layer is simultaneously etched in both first and second portions, using the hardmask patterns in the first portion to define features having a first width, and using the hardmask patterns and the sidewall spacers in the second portion to define features having a second width.

Abstract: A layer of doped oxide glass is deposited on a semiconductor device in a chemical vapor deposition chamber by reacting gaseous sources of silicon, ozone and at least one boron or phosphorus dopant in a carrier gas, the ozone being present in a ratio of about 9-15 weight percent of the carrier gas. The deposited layer of doped oxide glass contains no greater than about 4 weight percent each of boron and phosphorus concentration and is annealed at a temperature no greater than about 700° C. for a time sufficient to soften and outgas any residual moisture in the oxide glass layer and level the upper surface to a desired degree.

Abstract: An inert gas, such as helium, nitrogen, or argon, is used for pressurization and stabilization in a chemical vapor deposition process that occurs in an ambient temperature in excess of 400.degree. C. Using the inert gas in the pressurization and stabilization stages of the chemical vapor deposition process eliminates the formation of tungsten oxides on tungsten studs, lines and other devices in the substrate, thereby eliminating the variable contact resistance and other problems associated with tungsten oxides.

Abstract: A marker element is included in a deposition chamber. After use of the chamber to deposit films or coatings on workpieces, the chamber is cleaned to remove materials which may contaminate future processing of workpieces in the chamber. The composition of the gas exhausted from the chamber during the cleaning process is monitored, and a characteristic of the marker element is sensed. The cleaning gas is terminated in response to the sensed characteristic of the marker element having a predetermined value, such as a peak intensity or the return to a baseline value after peaking. The present invention effectively solves the problem of overcleaning or undercleaning the chamber based upon an estimated film thickness build up.