Abstract: A compact multi-element microphone has two rings of directional sensors. Using simple analog electronics, it delivers first-order outputs with low noise, wide bandwidth and tight transient response. The double-ring structure provides exceptionally high directional fidelity in the horizontal plane, while also keeping out-of-plane behaviour under control. This enables faithful capture of ambience, reflections and reverberation. A non-radial capsule arrangement moderates cavity resonances and reduces shading. Combined with digital electronics, the array can efficiently provide second-order and higher-order horizontal directivities that maintain their performance over a wider frequency range than with prior solutions. Outputs can be mono, two-channel stereo and multichannel surround sound. Applications include 360-degree immersive audio, with-height concert hall recording, and advanced voice capture using electronic steering of beams and nulls.

Abstract: A switching circuit, electrical energy converter, power management unit and energy harvesting system are described. Such apparatus is applicable to energy harvesting applications which involve a variety of transducers, either singly or simultaneously. The transducers may, for example, be photovoltaic, thermoelectric, piezoelectric, or electrodynamic. The described converters operate to convert impedances, voltages and currents. They incorporate inductive energy transfer elements, which are magnetically coupled. Different combinations of these energy transfer elements are used to obtain different conversion ratios, which can be referred to as “gears”. On the input side, having multiple gears enables easier and better matching to a wider variety of energy transducers. On the output side, it enables easier and better accommodation of a wider spread of energy storage voltages and of a wider variety of loads.

Abstract: A hybrid numeric-analog clock synchronizer for establishing a clock or carrier locked to a frequency reference. The clock synchronizer is typically a clock multiplier and a jitter attenuator. The reference may have a low update rate. The synchronizer achieves high jitter rejection, low phase noise and wide frequency range. It can be integrated on chip.

Abstract: There is disclosed a method of designing a panel assembly for a vibratory panel device, the assembly comprising a panel which supports vibrations and two or more transducers coupled to the panel to transmit vibrations to or receive vibrations from the panel. The method comprises: obtaining the number of transducers to be used in the assembly and their relative positions; obtaining relationships between drive signals to be applied to the respective transducers to provide a desired effect; determining an optimization criterion for the assembly that depends on the obtained relationships; and determining one or more parameters for the respective transducers that satisfy the optimization criterion. The one or more parameters may be selected from amplitudes of drive signals, spacing, activity, area, position, shape, dimension.

Abstract: There is disclosed a method of designing a panel assembly for a vibratory panel device, the assembly comprising a panel which supports vibrations and two or more transducers coupled to the panel to transmit vibrations to or receive vibrations from the panel. The method comprises: obtaining the number of transducers to be used in the assembly and their relative positions; obtaining relationships between drive signals to be applied to the respective transducers to provide a desired effect; determining an optimisation criterion for the assembly that depends on the obtained relationships; and determining one or more parameters for the respective transducers that satisfy the optimisation criterion. The one or more parameters may be selected from amplitudes of drive signals, spacing, activity, area, position, shape, dimension.

Abstract: A switching circuit, electrical energy converter, power management unit and energy harvesting system are described. Such apparatus is applicable to energy harvesting applications which involve a variety of transducers, either singly or simultaneously. The transducers may, for example, be photovoltaic, thermoelectric, piezoelectric, or electrodynamic. The described converters operate to convert impedances, voltages and currents. They incorporate inductive energy transfer elements, which are magnetically coupled. Different combinations of these energy transfer elements are used to obtain different conversion ratios, which can be referred to as “gears”. On the input side, having multiple gears enables easier and better matching to a wider variety of energy transducers. On the output side, it enables easier and better accommodation of a wider spread of energy storage voltages and of a wider variety of loads.

Abstract: There is disclosed a method of designing a panel assembly for a vibratory panel device, the assembly comprising a panel which supports vibrations and two or more transducers coupled to the panel to transmit vibrations to or receive vibrations from the panel. The method comprises: obtaining the number of transducers to be used in the assembly and their relative positions; obtaining relationships between drive signals to be applied to the respective transducers to provide a desired effect; determining an optimisation criterion for the assembly that depends on the obtained relationships; and determining one or more parameters for the respective transducers that satisfy the optimisation criterion. The one or more parameters may be selected from amplitudes of drive signals, spacing, activity, area, position, shape, dimension.

Abstract: A hybrid numeric-analog clock synchronizer, for establishing a clock or carrier locked to a timing reference. The clock may include a framing component. The reference may have a low update rate. The synchronizer achieves high jitter rejection, low phase noise and wide frequency range. It can be integrated on chip. It may comprise a numeric time-locked loop (TLL) with an analog phase-locked loop (PLL). Moreover a high-performance number-controlled oscillator (NCO), for creating an event clock from a master clock according to a period control signal. It processes edge times rather than period values, allowing direct control of the spectrum and peak amplitude of the justification jitter. Moreover a combined clock-and-frame asynchrony detector, for measuring the phase or time offset between composite signals. It responds e.g. to event clocks and frame syncs, enabling frame locking with loop bandwidths greater than the frame rate.

Abstract: A hybrid numeric-analog clock synchronizer, for establishing a clock or carrier locked to a timing reference. The clock may include a framing component. The reference may have a low update rate. The synchronizer achieves high jitter rejection, low phase noise and wide frequency range. It can be integrated on chip. It may comprise a numeric time-locked loop (TLL) with an analog phase-locked loop (PLL). Moreover a high-performance number-controlled oscillator (NCO), for creating an event clock from a master clock according to a period control signal. It processes edge times rather than period values, allowing direct control of the spectrum and peak amplitude of the justification jitter. Moreover a combined clock-and-frame asynchrony detector, for measuring the phase or time offset between composite signals. It responds e.g. to event clocks and frame syncs, enabling frame locking with loop bandwidths greater than the frame rate.

Abstract: There is disclosed a method of designing a panel assembly for a vibratory panel device, the assembly comprising a panel which supports vibrations and two or more transducers coupled to the panel to transmit vibrations to or receive vibrations from the panel. The method comprises: obtaining the number of transducers to be used in the assembly and their relative positions; obtaining relationships between drive signals to be applied to the respective transducers to provide a desired effect; determining an optimisation criterion for the assembly that depends on the obtained relationships; and determining one or more parameters for the respective transducers that satisfy the optimisation criterion. The one or more parameters may be selected from amplitudes of drive signals, spacing, activity, area, position, shape, dimension.

Abstract: A hybrid numeric-analog clock synchronizer, for establishing a clock or carrier locked to a timing reference. The clock may include a framing component. The reference may have a low update rate. The synchronizer achieves high jitter rejection, low phase noise and wide frequency range. It can be integrated on chip. It may comprise a numeric time-locked loop (TLL) with an analog phase-locked loop (PLL). Moreover a high-performance number-controlled oscillator (NCO), for creating an event clock from a master clock according to a period control signal. It processes edge times rather than period values, allowing direct control of the spectrum and peak amplitude of the justification jitter. Moreover a combined clock-and-frame asynchrony detector, for measuring the phase or time offset between composite signals. It responds e.g. to event clocks and frame syncs, enabling frame locking with loop bandwidths greater than the frame rate.

Abstract: A hybrid numeric-analog clock synchronizer, for establishing a clock or carrier locked to a timing reference. The clock may include a framing component. The reference may have a low update rate. The synchronizer achieves high jitter rejection, low phase noise and wide frequency range. It can be integrated on chip. It may comprise a numeric time-locked loop (TLL) with an analog phase-locked loop (PLL). Moreover a high-performance number-controlled oscillator (NCO), for creating an event clock from a master clock according to a period control signal. It processes edge times rather than period values, allowing direct control of the spectrum and peak amplitude of the justification jitter. Moreover a combined clock-and-frame asynchrony detector, for measuring the phase or time offset between composite signals. It responds e.g. to event clocks and frame syncs, enabling frame locking with loop bandwidths greater than the frame rate.

Abstract: There is disclosed a method of designing a panel assembly for a vibratory panel device, the assembly comprising a panel which supports vibrations and two or more transducers coupled to the panel to transmit vibrations to or receive vibrations from the panel. The method comprises: obtaining the number of transducers to be used in the assembly and their relative positions; obtaining relationships between drive signals to be applied to the respective transducers to provide a desired effect; determining an optimisation criterion for the assembly that depends on the obtained relationships; and determining one or more parameters for the respective transducers that satisfy the optimisation criterion. The one or more parameters may be selected from amplitudes of drive signals, spacing, activity, area, position, shape, dimension.

Abstract: There is provided a method of generating a primary effect in a vibratory panel device comprising at least N+M transducers connected to a panel, where N and M are integers greater than or equal to 1. Each transducer is electrically connected to signal processing circuitry and the signal processing circuitry is configured to receive signals from or provide signals to each transducer. The method comprises: obtaining N electrical signals to be applied respectively to N of the transducers to produce the primary effect; and processing the N electrical signals to produce M additional electrical signal(s), such that when the M signal(s) are applied to respective transducers other than the N transducers, a secondary effect is produced. The secondary effect may be for example cancellation of any audio output resulting from providing haptic feedback.

Abstract: A panel for use in a vibratory panel device comprises a substrate, a layer of electroactive material applied to the substrate and a layer of material applied to the electroactive material forming separate active areas whereby signals may be applied to or received from respective areas of the electroactive material, wherein the layer of material forming the active areas forms at least three active areas comprising at least two primary active areas and at least one secondary active area, the secondary active area being positioned relative to the two primary active areas such that one or both of the following conditions is provided: at least one secondary active area can be driven to at least partially offset any net displacement of the panel caused by driving two of the primary active areas; and the at least one secondary active area can sense vibrations of the panel affecting both of the two primary active areas.

Abstract: A hybrid numeric-analog clock synchronizer, for establishing a clock or carrier locked to a timing reference. The clock may include a framing component. The reference may have a low update rate. The synchronizer achieves high jitter rejection, low phase noise and wide frequency range. It can be integrated on chip. It may comprise a numeric time-locked loop (TLL) with an analog phase-locked loop (PLL). Moreover a high-performance number-controlled oscillator (NCO), for creating an event clock from a master clock according to a period control signal. It processes edge times rather than period values, allowing direct control of the spectrum and peak amplitude of the justification jitter. Moreover a combined clock-and-frame asynchrony detector, for measuring the phase or time offset between composite signals. It responds e.g. to event clocks and frame syncs, enabling frame locking with loop bandwidths greater than the frame rate.

Abstract: A hybrid numeric-analog clock synchronizer, for establishing a clock or carrier locked to a timing reference. The clock may include a framing component. The reference may have a low update rate. The synchronizer achieves high jitter rejection, low phase noise and wide frequency range. It can be integrated on chip. It may comprise a numeric time-locked loop (TLL) with an analog phase-locked loop (PLL). Moreover a high-performance number-controlled oscillator (NCO), for creating an event clock from a master clock according to a period control signal. It processes edge times rather than period values, allowing direct control of the spectrum and peak amplitude of the justification jitter. Moreover a combined clock-and-frame asynchrony detector, for measuring the phase or time offset between composite signals. It responds e.g. to event clocks and frame syncs, enabling frame locking with loop bandwidths greater than the frame rate.

Abstract: A hybrid numeric-analog clock synchronizer, for establishing a clock or carrier locked to a timing reference. The clock may include a framing component. The reference may have a low update rate. The synchronizer achieves high jitter rejection, low phase noise and wide frequency range. It can be integrated on chip. It may comprise a numeric time-locked loop (TLL) with an analog phase-locked loop (PLL). Moreover a high-performance number-controlled oscillator (NCO), for creating an event clock from a master clock according to a period control signal. It processes edge times rather than period values, allowing direct control of the spectrum and peak amplitude of the justification jitter. Moreover a combined clock-and-frame asynchrony detector, for measuring the phase or time offset between composite signals. It responds e.g. to event clocks and frame syncs, enabling frame locking with loop bandwidths greater than the frame rate.

Abstract: A hybrid numeric-analog clock synchronizer, for establishing a clock or carrier locked to a timing reference. The clock may include a framing component. The reference may have a low update rate. The synchronizer achieves high jitter rejection, low phase noise and wide frequency range. It can be integrated on chip. It may comprise a numeric time-locked loop (TLL) with an analog phase-locked loop (PLL). Moreover a high-performance number-controlled oscillator (NCO), for creating an event clock from a master clock according to a period control signal. It processes edge times rather than period values, allowing direct control of the spectrum and peak amplitude of the justification jitter. Moreover a combined clock-and-frame asynchrony detector, for measuring the phase or time offset between composite signals. It responds e.g. to event clocks and frame syncs, enabling frame locking with loop bandwidths greater than the frame rate.

Abstract: A communications bus operates using transition coding, for example NRZI coding, with transition-dominant signalling. That is, when the signal takes a first binary value, binary “1”, the component drives the bus line to its opposite state, and, when the signal takes a second binary value, binary “0”, the component does not actively drive the bus line. During arbitration, each arbitrating component writes a unique arbitrand onto the bus, and arbitration is lost by each component that writes a binary “0” when at least one other component writes a binary “1”. The components preferably do not use transition-dominant signalling when transmitting data payloads. For such traffic they actively drive the binary “0”s as well as binary “1”s.