Abstract: Systems and methods are disclosed for an audio processor that includes a clock detection circuit and a clock bypass circuit. According to various embodiments, the clock detection circuit can check and indicate the status of a main clock and upon detection of a loss of the main clock, the clock bypass circuit can switch the source of the main clock to an alternate source such as an on chip oscillator allowing the system to gracefully recover from the clock loss event.

Abstract: Systems and methods are disclosed for an audio processor that includes a clock detection circuit and a clock bypass circuit. According to various embodiments, the clock detection circuit can check and indicate the status of a main clock and upon detection of a loss of the main clock, the clock bypass circuit can switch the source of the main clock to an alternate source such as an on chip oscillator allowing the system to gracefully recover from the clock loss event.

Abstract: A system (20) for decoding a data stream allocated into data packets contains a control unit (54), a stream demultiplexer (26), audio and video decoders (38 and 40), a memory management unit (60), and audio and video input and output buffers. Upon demultiplexing and depacketizing the data packets without interrupting the control unit, the demultiplexer sends encoded audio and video data to the audio and video input buffers. Video messages dealing with video timing information and identifying where encoded video data is stored in the video input buffer are furnished by the demultiplexer for use by the control unit. Utilizing corresponding video instructions provided from the control unit, the video decoder decodes encoded video data to produce decoded video data supplied to the video output buffer. The audio decoder decodes encoded audio data to produce decoded audio data supplied to the audio output buffer. The memory management unit controls transfer of decoded audio data to and from the audio output buffer.

Abstract: An improved synchronization circuit has a numerically controlled oscillator (NCO) having an accumulator, a number line, and feedback line fed back from the accumulator output. The accumulator repeatedly adds the number represented on the number line and the number represented on the feedback line and feedbacks the result to the accumulator. The result rolls over to zero as would an odometer when it reaches a maximum value. When the number represented on number input is properly selected by, for example, a microprocessor, a data stream representing the most significant bit of the result has jitter. The synchronization circuit also has a phase-locked loop (PLL) configured to receive the data stream of the most significant bit. The frequency of the most significant bit stream and the frequency of the jitter on that bit stream are controlled by the number at the number input. The number is chosen to maximize the jitter frequency and thus maximize jitter attenuation through the PLL.

Abstract: The present invention provides a method and apparatus for providing video output phase control in a decoder. In particular, the present invention provides a decoder that precisely aligns output of video display data with a time stamp associated with the video display data and thereby allows for efficient usage of compressed video buffer memory in the decoder. In one embodiment, the decoder includes a video output processor for displaying video data and a timer connected to the video output processor for providing video output phase control. A method is also provided for providing video output phase control in the decoder.