Patents by Inventor Christopher Kawamura
Christopher Kawamura has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11176978Abstract: Apparatuses and methods for reducing row address (RAS) to column address (CAS) delay (tRCD) are disclosed. In some examples, tRCD may be reduced by providing a non-zero offset voltage to a target wordline at an earlier time, such as during a threshold voltage compensation phase of a sense operation. Setting the wordline to a non-zero offset voltage at an earlier time may reduce a time for the wordline to reach an activation voltage, which may reduce tRCD. In other examples, protection against row hammer attacks during precharge phases may be improved by setting the wordline to the non-zero offset voltage.Type: GrantFiled: September 28, 2020Date of Patent: November 16, 2021Assignee: Micron Technology, Inc.Inventor: Christopher Kawamura
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Patent number: 11120847Abstract: Apparatuses and methods for reducing row address (RAS) to column address (CAS) delay are disclosed. An example apparatus includes a memory including a memory cell coupled to a first digit line in response to a wordline being set to an active state, and a sense amplifier configured to, during a sense operation, couple a first gut node to the first digit line and couple a second gut node to a second digit line in response to an isolation signal. The sense amplifier is further configured to, after the first gut node is coupled to the first digit line and the second gut node is coupled to the second digit line, drive the first digit line to a first sense voltage of a first control signal and drive the second digit line to a second sense voltage of a second control signal based on a data state of the memory cell.Type: GrantFiled: January 21, 2020Date of Patent: September 14, 2021Inventors: Christopher Kawamura, Tae H. Kim
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Publication number: 20210027821Abstract: Apparatuses and methods for reducing row address (RAS) to column address (CAS) delay (tRCD) are disclosed. In some examples, tRCD may be reduced by providing a non-zero offset voltage to a target wordline at an earlier time, such as during a threshold voltage compensation phase of a sense operation. Setting the wordline to a non-zero offset voltage at an earlier time may reduce a time for the wordline to reach an activation voltage, which may reduce tRCD. In other examples, protection against row hammer attacks during precharge phases may be improved by setting the wordline to the non-zero offset voltage.Type: ApplicationFiled: September 28, 2020Publication date: January 28, 2021Applicant: Micron Technology, Inc.Inventor: Christopher Kawamura
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Patent number: 10902899Abstract: Apparatuses and methods for reducing row address (RAS) to column address (CAS) delay are disclosed. An example apparatus includes a memory including a memory cell coupled to a first digit line in response to a wordline being set to an active state and a sense amplifier coupled to the first digit line and to a second digit line. The sense amplifier is configured to perform a threshold voltage compensation operation to bias the first digit line and the second digit line based on a threshold voltage difference between at least two circuit components of the sense amplifier. The apparatus further comprising a decoder circuit coupled to the wordline and to the sense amplifier. In response to an activate command, the decoder circuit is configured to initiate the threshold voltage compensation operation and, during the threshold voltage compensation operation, to the set the wordline to the active state.Type: GrantFiled: December 27, 2019Date of Patent: January 26, 2021Assignee: Micron Technology, inc.Inventor: Christopher Kawamura
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Patent number: 10839871Abstract: Apparatuses and methods for operation of a sense amplifier during a power-down operation. The example apparatus may include a sense amplifier including of a transistor coupled between a digit line and a gut node of the sense amplifier. While a wordline coupled to a memory cell is activated, in response to entering a power-down mode, the transistor is disabled to decouple a digit line coupled to the memory cell from the gut node, which reduces leakage current in the sense amplifier.Type: GrantFiled: February 5, 2020Date of Patent: November 17, 2020Assignee: Micron Technology, Inc.Inventor: Christopher Kawamura
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Patent number: 10796743Abstract: Methods, systems, and devices for operating a ferroelectric memory cell or cells are described. A ferroelectric memory cell may be used to store a logic state. The capacitance of a digit line of the ferroelectric memory cell may be dynamically increased prior to, and during a portion of, a read operation used to determine a stored logic state of the cell. The capacitance may be increased by leveraging intrinsic capacitance of digit lines of the array—e.g., by shorting one digit line to another digit line. Increasing the capacitance of the digit line may increase the signal on the digit line that is sensed during the read operation.Type: GrantFiled: November 8, 2018Date of Patent: October 6, 2020Inventors: Christopher Kawamura, Charles Ingalls, Scott Derner
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Patent number: 10790000Abstract: Apparatuses and methods for reducing row address (RAS) to column address (CAS) delay (tRCD) are disclosed. In some examples, tRCD may be reduced by providing a non-zero offset voltage to a target wordline at an earlier time, such as during a threshold voltage compensation phase of a sense operation. Setting the wordline to a non-zero offset voltage at an earlier time may reduce a time for the wordline to reach an activation voltage, which may reduce tRCD. In other examples, protection against row hammer attacks during precharge phases may be improved by setting the wordline to the non-zero offset voltage.Type: GrantFiled: November 14, 2018Date of Patent: September 29, 2020Assignee: Micron Technology, Inc.Inventor: Christopher Kawamura
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Publication number: 20200176034Abstract: Apparatuses and methods for operation of a sense amplifier during a power-down operation. The example apparatus may include a sense amplifier including of a transistor coupled between a digit line and a gut node of the sense amplifier. While a wordline coupled to a memory cell is activated, in response to entering a power-down mode, the transistor is disabled to decouple a digit line coupled to the memory cell from the gut node, which reduces leakage current in the sense amplifier.Type: ApplicationFiled: February 5, 2020Publication date: June 4, 2020Applicant: Micron Technology, Inc.Inventor: Christopher Kawamura
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Patent number: 10672435Abstract: Apparatuses for signal boost are disclosed. An example apparatus includes: first and second digit lines coupled to memory cells; a sense amplifier including: first and second transistors having gates operatively coupled to the first digit line and drains coupled to a first node, sources of the first and second transistors coupled to first and second control lines providing first and second power supply voltage respectively; and third and fourth transistors having gates coupled to the second digit line and drains coupled to a second node, sources of the third and fourth transistors coupled to the first and second control lines respectively; a power line coupled to the first node and the second node; and a power switch providing either the first power supply voltage or a third power supply voltage smaller than the first power supply voltage to the power line.Type: GrantFiled: January 24, 2019Date of Patent: June 2, 2020Assignee: Micron Technology, Inc.Inventors: Charles Ingalls, Christopher Kawamura
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Publication number: 20200160893Abstract: Apparatuses and methods for reducing row address (RAS) to column address (CAS) delay are disclosed. An example apparatus includes a memory including a memory cell coupled to a first digit line in response to a wordline being set to an active state, and a sense amplifier configured to, during a sense operation, couple a first gut node to the first digit line and couple a second gut node to a second digit line in response to an isolation signal. The sense amplifier is further configured to, after the first gut node is coupled to the first digit line and the second gut node is coupled to the second digit line, drive the first digit line to a first sense voltage of a first control signal and drive the second digit line to a second sense voltage of a second control signal based on a data state of the memory cell.Type: ApplicationFiled: January 21, 2020Publication date: May 21, 2020Applicant: MICRON TECHNOLOGY, INC.Inventors: Christopher Kawamura, Tae H. Kim
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Publication number: 20200152249Abstract: Apparatuses and methods for reducing row address (RAS) to column address (CAS) delay (tRCD) are disclosed. In some examples, tRCD may be reduced by providing a non-zero offset voltage to a target wordline at an earlier time, such as during a threshold voltage compensation phase of a sense operation. Setting the wordline to a non-zero offset voltage at an earlier time may reduce a time for the wordline to reach an activation voltage, which may reduce tRCD. In other examples, protection against row hammer attacks during precharge phases may be improved by setting the wordline to the non-zero offset voltage.Type: ApplicationFiled: November 14, 2018Publication date: May 14, 2020Applicant: Micron Technology, Inc.Inventor: Christopher Kawamura
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Publication number: 20200143863Abstract: Methods, systems, and devices for periphery fill and localized capacitance are described. A memory array may be fabricated with certain containers connected to provide capacitance rather than to operate as memory cells. For example, a memory cell having one or two transistors, or other switching components, and one capacitor, such as a ferroelectric or dielectric capacitor, may be electrically isolated from one or more containers sharing a common access line, and the isolated containers may be used as capacitors. The capacitors may be used for filtering in some examples. Or the capacitance may be used to boost or regulate voltage in, for example, support circuitry.Type: ApplicationFiled: January 2, 2020Publication date: May 7, 2020Inventors: Christopher Kawamura, Scott James Derner
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Publication number: 20200135249Abstract: Apparatuses and methods for reducing row address (RAS) to column address (CAS) delay are disclosed. An example apparatus includes a memory including a memory cell coupled to a first digit line in response to a wordline being set to an active state and a sense amplifier coupled to the first digit line and to a second digit line. The sense amplifier is configured to perform a threshold voltage compensation operation to bias the first digit line and the second digit line based on a threshold voltage difference between at least two circuit components of the sense amplifier. The apparatus further comprising a decoder circuit coupled to the wordline and to the sense amplifier. In response to an activate command, the decoder circuit is configured to initiate the threshold voltage compensation operation and, during the threshold voltage compensation operation, to the set the wordline to the active state.Type: ApplicationFiled: December 27, 2019Publication date: April 30, 2020Applicant: MICRON TECHNOLOGY, INC.Inventor: Christopher Kawamura
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Patent number: 10636472Abstract: Methods, systems, and devices for operating a ferroelectric memory cell or cells are described. The magnitude of a voltage applied across a ferroelectric capacitor may be dynamically increased during a write operation. For example, a memory cell may be selected for a write operation, and a voltage may be applied to a digit line corresponding to the memory cell during the write operation. An additional charge may be transferred to the digit line—e.g., from an energy storage component, such as a capacitor, that is in electronic communication with the digit line. In turn, the voltage across the ferroelectric capacitor of the memory cell may be increased.Type: GrantFiled: June 13, 2019Date of Patent: April 28, 2020Assignee: Micron Technology, Inc.Inventors: Christopher Kawamura, Howard Kirsch
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Patent number: 10566036Abstract: Apparatuses and methods for reducing sense amplifier leakage current during an active power-down are disclosed. An example apparatus includes a memory that includes a memory cell and a first digit line and a second digit line. The memory cell is coupled to the first digit line in response to activation of a wordline coupled the memory cell. The example apparatus further includes a sense amplifier comprising of a first transistor coupled between the first digit line and a first gut node of the sense amplifier and a second transistor coupled between the second digit line and a second gut node of the sense amplifier. While the wordline is activated, in response to entering a power-down mode, the first transistor is disabled to decouple the first digit line from the first gut node and the second transistor is disabled to decouple the second digit line from the second gut node.Type: GrantFiled: June 15, 2018Date of Patent: February 18, 2020Assignee: Micron Technology, Inc.Inventor: Christopher Kawamura
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Patent number: 10541008Abstract: Apparatuses and methods for reducing row address (RAS) to column address (CAS) delay are disclosed. An example apparatus includes a memory including a memory cell coupled to a first digit line in response to a wordline being set to an active state, and a sense amplifier configured to, during a sense operation, couple a first gut node to the first digit line and couple a second gut node to a second digit line in response to an isolation signal. The sense amplifier is further configured to, after the first gut node is coupled to the first digit line and the second gut node is coupled to the second digit line, drive the first digit line to a first sense voltage of a first control signal and drive the second digit line to a second sense voltage of a second control signal based on a data state of the memory cell.Type: GrantFiled: June 25, 2018Date of Patent: January 21, 2020Assignee: Micron Technology, Inc.Inventors: Christopher Kawamura, Tae H. Kim
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Patent number: 10522205Abstract: Apparatuses and methods for reducing row address (RAS) to column address (CAS) delay are disclosed. An example apparatus includes a memory including a memory cell coupled to a first digit line in response to a wordline being set to an active state and a sense amplifier coupled to the first digit line and to a second digit line. The sense amplifier is configured to perform a threshold voltage compensation operation to bias the first digit line and the second digit line based on a threshold voltage difference between at least two circuit components of the sense amplifier. The apparatus further comprising a decoder circuit coupled to the wordline and to the sense amplifier. In response to an activate command, the decoder circuit is configured to initiate the threshold voltage compensation operation and, during the threshold voltage compensation operation, to the set the wordline to the active state.Type: GrantFiled: June 20, 2018Date of Patent: December 31, 2019Assignee: Micron Technology, Inc.Inventor: Christopher Kawamura
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Publication number: 20190392872Abstract: Apparatuses and methods for reducing row address (RAS) to column address (CAS) delay are disclosed. An example apparatus includes a memory including a memory cell coupled to a first digit line in response to a wordline being set to an active state, and a sense amplifier configured to, during a sense operation, couple a first gut node to the first digit line and couple a second gut node to a second digit line in response to an isolation signal. The sense amplifier is further configured to, after the first gut node is coupled to the first digit line and the second gut node is coupled to the second digit hue, drive the first digit line to a first sense voltage of a first control signal and drive the second digit line to a second sense voltage of a second control signal based on a data state of the memory cell.Type: ApplicationFiled: June 25, 2018Publication date: December 26, 2019Applicant: MICRON TECHNOLOGY, INC.Inventors: Christopher Kawamura, Tae H. Kim
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Publication number: 20190392877Abstract: Apparatuses and methods for reducing row address (RAS) to column address (CAS) delay are disclosed. An example apparatus includes a memory including a memory cell coupled to a first digit line in response to a wordline being set to an active state and a sense amplifier coupled to the first digit line and to a second digit line. The sense amplifier is configured to perform a threshold voltage compensation operation to bias the first digit line and the second digit line based on a threshold voltage difference between at least two circuit components of the sense amplifier. The apparatus further comprising a decoder circuit coupled to the wordline and to the sense amplifier. In response to an activate command, the decoder circuit is configured to initiate the threshold voltage compensation operation and, during the threshold voltage compensation operation, to the set the wordline to the active state.Type: ApplicationFiled: June 20, 2018Publication date: December 26, 2019Applicant: MICRON TECHNOLOGY, INC.Inventor: Christopher Kawamura
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Publication number: 20190385649Abstract: Apparatuses and methods for reducing sense amplifier leakage current during an active power-down are disclosed. An example apparatus includes a memory that includes a memory cell and a first digit line and a second digit line. The memory cell is coupled to the first digit line in response to activation of a wordline coupled the memory cell. The example apparatus further includes a sense amplifier comprising of a first transistor coupled between the first digit line and a first gut node of the sense amplifier and a second transistor coupled between the second digit line and a second gut node of the sense amplifier. While the wordline is activated, in response to entering a power-down mode, the first transistor is disabled to decouple the first digit line from the first gut node and the second transistor is disabled to decouple the second digit line from the second gut node.Type: ApplicationFiled: June 15, 2018Publication date: December 19, 2019Applicant: MICRON TECHNOLOGY, INC.Inventor: Christopher Kawamura