Abstract: An inexpensive synchronous detection module is disclosed for a sideband signal receiver that provides for flexibility in design of the tuner. The detection module is adaptable to detection of upper or lower sideband signals. One embodiment includes an analog-to-digital converter, a Hilbert transform filter, a sideband selection switch, a complex multiplier, a carrier recovery. loop, a matched filter, and a decimator. The analog-to-digital converter oversamples an intermediate frequency (IF) signal from the tuner, and the Hilbert transform filter generates a Hilbert transform of the digital IF signal. An analytic IF signal can be generated from the digital IF signal by multiplying the Hilbert transform of the digital IF signal by j(=sqrt(−1)), and adding the resulting imaginary-valued signal to the digital IF signal. The sideband selection switch can “flip” the analytic IF signal by inverting the imaginary-valued signal.

Abstract: Digital interference rejection of a signal is accomplished by first converting the signal to digital. Then a second signal is generated and mixed with the first signal. This combined signal is then filtered. The signal can then be scaled as needed, resulting in a finely tuned, interference free signal.

Abstract: Digital interference rejection of a signal is accomplished by first converting the signal to digital. Then a second signal is generated and mixed with the first signal. This combined signal is then filtered. The signal can then be scaled as needed, resulting in a finely tuned, interference free signal.

Abstract: An improved satellite receiver front end architecture having a tuner chip and a demodulator/decoder chip. The tuner chip includes a lowpass filter having a configurable cutoff frequency, and the tuner chip uses a frequency signal to provide accurate adjustment of the cutoff frequency. A clock signal having a clock frequency is converted into a control voltage which determines the cutoff frequency of the lowpass filter. Consequently, the cutoff frequency may be increased by increasing the clock frequency, or decreased by decreasing the clock frequency. This configuration provides for improved cutoff frequency control in the presence of signal interference.

Abstract: An improved DBS receiver front end architecture having a tuner chip and a demodulator/decoder chip. The tuner chip and the demodulator/decoder chip each include portions of a digital tuning frequency synthesizer. The frequency synthesizer comprises one or more digital counters which are implemented on the demodulator/decoder chip, and an oscillator which is implemented on the tuner chip. This advantageously avoids digital noise interference with the tuner chip while providing a reduced part count. Briefly, the present invention concerns a DBS receiver front end which includes a tuner chip and a demodulator/decoder chip which cooperate to perform a frequency synthesis function. The tuner chip has a tuning oscillator coupled to a tank circuit having an adjustable resonance frequency, and a downconverter coupled to receive a tuning frequency signal provided by the tuning oscillator.

Abstract: The problems outlined above are in large part solved by an improved DBS receiver front end architecture having a tuner chip and a demodulator/decoder chip. The front end includes a frequency synthesizer with an externally configurable charge pump on the tuner chip. The charge pump is coupled to a tank circuit having an adjustable resonance frequency. The resonance frequency can be adjusted over an entire octave by controlling the reverse bias voltage on a pair of varactors. A charge pump with a configurable gain is used to provide a control voltage to the tank circuit to provide a constant phase locked loop response over the frequency range of the tank circuit. Broadly speaking, the present invention concerns a DBS receiver front end which includes a tuner chip and a demodulator/decoder chip. The tuner chip is coupled to receive a receive signal and convert it to a baseband signal. The tuner chip includes an externally configurable charge pump, a tuning oscillator, and a downconverter.

Abstract: A DBS receiver front end which includes a tuner chip and a demodulator/decoder chip. The tuner chip converts a receive signal to a baseband signal using a tuning frequency signal generated from a tank circuit. The design of a package for the tuner chip maximally spaces the pins associated with high frequency signals by placing them on opposite sides of the chip (in the case of two high frequency signal sources) or (in the case of three high frequency signal sources) in a triangle formation with widely spaced vertices wherein at least two of the pins are adjacent to corners of the package. For two or more high frequency signal sources, a good determination of pin locations can be determined according to the formula P.sub.i =C+i.multidot..left brkt-bot.N/M.right brkt-bot., i=1, . . . , M, where P.sub.i are the pin numbers, N is a total number of pins around the perimeter of the package, M is a total number of the high frequency signal sources, and C is an offset number.

Abstract: The present invention concerns a DBS receiver which serves to combine the functions of variable rate demodulation, convolutional decoding, de-interleaving and block decoding. The demodulation stage includes a novel circuit for clock synchronization. By combining the functions of these components this device provides a higher level of utility as measured in terms of reliability, simplicity, flexibility, cost effectiveness, and integration of board layout while maintaining optimum-quality signal processing.

Abstract: An apparatus and method for suppressing intermodulation noise in a radio frequency power amplifier. Intermodulation noise suppression is achieved by use of an amplitude limiter connected to the signal source and a shaping filter connected between the amplitude limiter and the power amplifier. The shaping filter may be a band-stop notch filter which attenuates intermodulation noise in a selected radio band or a bandpass filter which attenuates all out-of-band intermodulation noise. The intermodulation noise suppression of this invention causes the signal entering the power amplifier to be characterized by (1) a low peak-to-average envelope distribution and (2) low spectral content in the radio frequency bands to be protected.

Abstract: An improved DBS receiver front end architecture having a voltage controlled oscillator for frequency synthesis. The voltage controlled oscillator includes a tank circuit having an adjustable resonance frequency which may be varied over an octave. A tuning oscillator drives the tank circuit and provides a signal having that resonance frequency to a range extender which provides a tuning frequency. When enabled, the range extender doubles the input frequency, and when disabled, simply passes the input frequency through. A feedback path provides a control voltage to the tank circuit to adjust the resonance frequency and thereby cause the tuning frequency to be a multiple of a reference frequency. The range extender extends the tuning frequency range over two octaves without a loss of frequency resolution. Broadly speaking, the present invention contemplates a DBS receiver front end which includes a tuner chip and a demodulator/decoder chip.

Abstract: A DBS receiver front end which includes a tuner chip and a demodulator/decoder chip having digital interface signals. The tuner chip is configured to receive the digital signals at a reduced peak-to-peak amplitude to reduce the digital interference noise in the tuner chip. The digital signals may also have a limited slew rate to further reduce the digital interference noise. The tuner chip is configured to convert a receive signal to a baseband signal, and the demodulator/decoder chip is configured to convert the baseband signal to a decoded signal.

Abstract: A concatenated three layer Viterbi, Reed-Solomon/Deinterleaver and Descrambler forward error correction decoder may be utilized in digital video and audio systems, and for direct broadcast satellite applications. The digital signal may be a compressed video and audio signal transmitted from a direct broadcast satellite. Acquisition for three layers of synchronization are required, but once all three layers are in-sync, down stream data synchronization monitoring will suffice so that upstream synchronization monitoring can be disabled thus improving system robustness to noise bursts and false synchronization on false sync bytes generated at the transmission encoder during non-changing data signal conditions.

Abstract: An improved DBS receiver front end architecture having a tuner chip and a demodulator/decoder chip. The tuner chip has reduced-power features which allow the incorporation of an on-chip voltage regulator. The tuner chip is a direct conversion tuner with on-chip tuning frequency generation and reduced power interface signals. The on-chip voltage regulator provides a constant power supply for nonlinear components of the tuner and frequency generation circuitry to minimize phase noise. Broadly speaking, the present invention concerns a DBS receiver front end which includes a tuner chip and a demodulator/decoder chip. The tuner chip includes an on-chip voltage regulator, in addition to a tuning oscillator, a charge pump, a downconverter, and a lowpass filter. The on-chip voltage regulator is operable to provide a stable power supply to the tuning oscillator and the charge pump.

Abstract: A DBS receiver front end which converts the received signal directly to the baseband representation and maintains a high performance with a new techniques for tracking and counteracting frequency drift, and correcting I/Q angular error and amplitude imbalance. The DBS receiver front end comprises a tuner and a demodulator/decoder. The tuner receives a high frequency signal and converts it to a baseband signal having a frequency offset error. In one embodiment, the DBS receiver front end includes a demodulator/decoder which digitally performs I/Q angular error correction. The tuner converts the high frequency signal to a baseband signal having an in-phase and a quadrature-phase component. Ideally, the components are separated by ninety degrees, but typically an angular error exists. The demodulator/decoder includes an adaptive equalizer for correcting the angular error. Having the equalizer allows for relaxed tolerances in the tuner.