Abstract: Very long instruction word (VLIW) instruction processing using a reduced-width processor is disclosed. In a particular embodiment, a VLIW processor includes a control circuit configured to receive a VLIW packet that includes a first number of instructions and to distribute the instructions to a second number of instruction execution paths. The first number is greater than the second number. The VLIW processor also includes physical registers configured to store results of executing the instructions and a register renaming circuit that is coupled to the control circuit.

Abstract: A device includes a processor coupled to a memory. The processor is configured to assign distinct domain identifiers to each of multiple software threads. The processor is also configured to control operation of one or more components of the processor based on a number of memory transactions associated with a domain identifier.

Abstract: Various embodiments include methods and devices for managing optional commands. Some embodiments may include receiving an optional command from an optional command request device, determining whether the optional command can be implemented, and transmitting, to the optional command request device, an optional command no data response in response to determining that the optional command cannot be implemented.

Abstract: Very long instruction word (VLIW) instruction processing using a reduced-width processor is disclosed. In a particular embodiment, a VLIW processor includes a control circuit configured to receive a VLIW packet that includes a first number of instructions and to distribute the instructions to a second number of instruction execution paths. The first number is greater than the second number. The VLIW processor also includes physical registers configured to store results of executing the instructions and a register renaming circuit that is coupled to the control circuit.

Abstract: An intelligent tile-based memory bandwidth management solution executed by an address aperture, such as a compression address aperture, services linearly addressed data requests (read requests and write requests) from a processor to data stored in a memory component having a tile-based address structure. For read requests, the aperture stores previously read tiles (full or partial) in a tile-aware cache and then seeks to service future read requests from the cache instead of the long-term memory component. For write requests, the aperture stores the write data in the tile-aware cache and assembles the data with write data from other write requests so that full tile data writes to the long-term memory may be achieved in lieu of excessive partial-tile writes.

Abstract: Very long instruction word (VLIW) instruction processing using a reduced-width processor is disclosed. In a particular embodiment, a VLIW processor includes a control circuit configured to receive a VLIW packet that includes a first number of instructions and to distribute the instructions to a second number of instruction execution paths. The first number is greater than the second number. The VLIW processor also includes physical registers configured to store results of executing the instructions and a register renaming circuit that is coupled to the control circuit.

Abstract: Very long instruction word (VLIW) instruction processing using a reduced-width processor is disclosed. In a particular embodiment, a VLIW processor includes a control circuit configured to receive a VLIW packet that includes a first number of instructions and to distribute the instructions to a second number of instruction execution paths. The first number is greater than the second number. The VLIW processor also includes physical registers configured to store results of executing the instructions and a register renaming circuit that is coupled to the control circuit.

Abstract: Improved timeout table mechanism are disclosed. By way of example, a method for providing timeout delays for data queues in a processing system includes the following steps. A timeout structure is maintained. The timeout structure includes two or more groups, each group including two or more bins, each bin having a range of timeout delay values associated therewith, each group having a weight associated therewith, the weight of each group being based on a rate and a quantity of queues assignable to each group. A timeout delay value to be assigned to a data queue in the processing system is selected.

Abstract: A switching system for a data traffic network. A plurality of line cards provide input and output connections to a plurality of data lines and further are connected to at least two switch fabrics, one of which is designated the active switch fabric and the other designated the standby switch fabric. Data traffic is switched between the plurality of input and output line cards by the active switch fabric. When it is desired to change the active switch fabric assignment, for example due to a fault in the switch fabric, data transmissions into the active switch fabric are terminated and a drain timer is started. When the drain timer times out or the active switch provides an indication that it is empty, the active switch fabric assignment is swapped to the standby switch fabric and data is then switched through the newly assigned active switch fabric.

Abstract: Improved timeout table mechanism are disclosed. By way of example, a method for providing timeout delays for data queues in a processing system includes the following steps. A timeout structure is maintained. The timeout structure includes two or more groups, each group including two or more bins, each bin having a range of timeout delay values associated therewith, each group having a weight associated therewith, the weight of each group being based on a rate and a quantity of queues assignable to each group. A timeout delay value to be assigned to a data queue in the processing system is selected.

Abstract: Techniques for the design and use of a digital signal processor, including processing transmissions in a communications (e.g., CDMA) system. Power-efficient sign extension for Booth multiplication processes involves applying a sign bit in a Booth multiplication tree. The sign bit allows the Booth multiplication process to perform a sign extension step. This further involves one-extending a predetermined partial product row of the Booth multiplication tree using a sign bit for preserving the correct sign of the predetermined partial product row. The process and system resolve the signal value of the sign bit by generating a sign-extension bit in the Booth multiplication tree. The sign-extension bit is positioned in a carry-out column to extend the product of the Booth multiplication process. Then, the method and system form a final product from the Booth multiplication tree by adding the carry-out value to the sign bit positioned at least a predetermined column of the Booth multiplication tree.

Abstract: Techniques for the design and use of a digital signal processor, including processing transmissions in a communications (e.g., CDMA) system. A modified Booth multiplication system and process determine a multiplicand, A, and a multiplier, B. Radix-m, (e.g., radix-4) Booth recoding on B generates “n” multiplication factors, where “n,” an integer, is approximating one half of the number of the multiplier bits. “n” partial products are generated using the “n” multiplication factors as multipliers of A. Then, a multiplication tree is formed using radix-m Booth encoding. The multiplication tree includes multiplier bits associated to generate a multiplication factors. In the event of a negative multiplication factor, a two's complement of A is formed by inverting the bits of A and associating a sticky “1” to complete the two's complementation. Furthermore, multiplication factors are reduced in multiple stages to a form sum and carry components of a pre-determined length.

Abstract: A system and method is disclosed and includes an execution unit that can be used to count the leading zeros in a data word. During operation, the execution unit can receive a data word that has a width of 2 to the Nth power. Further, the execution unit can sign extend the data word to a temporary data word that has a width of 2 to the Mth power, wherein M is greater than N. The temporary data word can be input to a counter that has a width of 2 to the Mth power and the counter can count the leading zeros within the temporary data word to get a result.

Abstract: A method of completing a two's complement operation includes receiving a plurality of byte values and splitting the plurality of byte values into a first portion and a second portion. Further, the method includes inputting the first portion to a first segment of a first four-to-two compressor, performing a first four-to-two compression operation on the first portion to generate a first set of results having a first row and a second row that is offset one bit from the first row, and carrying in a first value of one to complete a first two's complement operation. The method also includes inputting the second portion to a second segment of a second four-to-two compressor and adding two values of one immediately to the right of the second portion in order to carry in a second value of one to the second portion to complete a second two's complement operation.

Abstract: A method is disclosed for free memory allocation in a linked list memory scheme. Free lists are link lists designating available memory for data storage. This method leverages the ability to read memory while concurrently updating a pointer to the next location. Multiple free lists are used to reduce the number of cycles necessary to allocate memory. The number of entries in each free list is tracked. When memory becomes available, it is spliced into the shortest free list to achieve balance between the free lists. The free list structure disclosed consists of head, head +1, and tail pointers where head +1 is the next logical address pointed to from the head pointer location. The free list consists only of the head and tail pointers. Each link list structure of memory to be freed contains the head, head +1, and tail pointers. This allows us to simultaneously allocate and free with only 1 memory cycle.

Abstract: An apparatus and method for moving and/or resizing logical buffers that comprise a memory space without the loss of data. Each buffer comprises a linear and contiguous set of storage locations, and operates according to a FIFO priority scheme, using a read address pointer to indicate the location from which data is read from the buffer and a write address pointer indicating the address into which data is written. A buffer is relocated or resized within the memory space by changing the base location address (defining the lowest storage location comprising the buffer) and/or the top location address (defining the highest memory location within the buffer) into free storage locations. To accomplish this relocation or resizing without the loss of data, the read address is first checked to determine if it bears an appropriate relationship to the new base and top memory locations.

Abstract: A system and method for memory management in a high-speed network environment. Multiple packets are interleaved in data streams and sent to a Memory Manager System. Read and write requests are queued in FIFO buffers. Subsets of these requests are grouped and ordered to optimize processing. This method employs a special arbitration scheme between read and write accesses. Read and write requests are treated as atomic. Memory bank selection is optimized for the request being processed. Alternating between memory bank sets is done to minimize bank conflicts. Link list updates are pipelined. Multiple independent link lists may be supported with the inclusion of a link list identifier. Arbitration between read and write requests continues until the group is exhausted. Then, processing is repeated for the next requests in the BRAM (buffer memories).

Abstract: A switching system for a data traffic network. A plurality of line cards provide input and output connections to a plurality of data lines and further are connected to at least two switch fabrics, one of which is designated the active switch fabric and the other designated the standby switch fabric. Data traffic is switched between the plurality of input and output line cards by the active switch fabric. When it is desired to change the active switch fabric assignment, for example due to a fault in the switch fabric, data transmissions into the active switch fabric are terminated and a drain timer is started. When the drain timer times out or the active switch provides an indication that it is empty, the active switch fabric assignment is swapped to the standby switch fabric and data is then switched through the newly assigned active switch fabric.

Abstract: A system and method for memory management in a high-speed network environment. Multiple packets are interleaved in data streams and sent to a Memory Manager System. Read and write requests are queued in FIFO buffers. Subsets of these requests are grouped and ordered to optimize processing. This method employs a special arbitration scheme between read and write accesses. Read and write requests are treated as atomic. Memory bank selection is optimized for the request being processed. Alternating between memory bank sets is done to minimize bank conflicts. Link list updates are pipelined. Multiple independent link lists may be supported with the inclusion of a link list identifier. Arbitration between read and write requests continues until the group is exhausted. Then, processing is repeated for the next requests in the BRAM (buffer memories).

Abstract: A method is disclosed for free memory allocation in a linked list memory scheme. Free lists are link lists designating available memory for data storage. This method leverages the ability to read memory while concurrently updating a pointer to the next location. Multiple free lists are used to reduce the number of cycles necessary to allocate memory. The number of entries in each free list is tracked. When memory becomes available, it is spliced into the shortest free list to achieve balance between the free lists. The free list structure disclosed consists of head, head +1, and tail pointers where head +1 is the next logical address pointed to from the head pointer location. The free list consists only of the head and tail pointers. Each link list structure of memory to be freed contains the head, head +1, and tail pointers. This allows us to simultaneously allocate and free with only 1 memory cycle.