Abstract: A communications session, e.g., a call, is established between the wireless terminal and a base station. Reception of at least one channel over respective diverse reception paths in the wireless terminal is measured during at least one transmission gap in the communications session. The at least one transmission gap may include, for example, a handover candidate channel evaluation transmission gap and/or an interfrequency measurement gap. Measurement of the selection diverse reception paths may be preceded by transitioning to a compressed mode of communications between the base station and the terminal, and the at least one transmission gap may include a transmission gap associated with the compressed mode.

Abstract: A transceiver (100) includes a synthesizer (400, 500, 600) which includes a single phase locked loop (406) for generating both a transmit offset signal and a receive second local oscillator (LO) signal for use by the transceiver. A single voltage controlled oscillator 424 provides oscillator signals for both modes. A prescaler (428) in the phase locked loop keeps the tuning distance of the VCO small. The resulting transceiver and radio including the transceiver has reduced parts count and current drain and is smaller in size then previous equipment with the same functionality.

Abstract: When attempting to reduce the number of battery cells in cellular telephones, a frequency synthesizer or phase locked loop located within the cellular telephone will output an increasing amount of noise. In order to reduce the amount of noise output when reducing the number of battery cells in such systems, the present invention employs a voltage step up device which effectively increases the voltage range of a voltage controlled oscillator within the frequency synthesizer. To further reduce the noise, the voltage step-up unit is employed with passive elements thus reducing the noise further and optimizing the output of the phase locked loop. Several different designs are discussed to further reduce space requirements and increase programmability of the system.

Abstract: A phase lock loop circuit comprising a reference frequency divider, wherein the divisor increases until the desired operating frequency is reached. The input frequency is delivered to a summing circuit that sums the input frequency with an output frequency. The resultant frequency is delivered to a phase comparator, which generates an error voltage. The error voltage is used to drive a voltage-controlled oscillator to generate an output frequency. A divisor in the voltage-controlled oscillator increases synchronously with the reference frequency divider until the desired operating frequency is reached.

Abstract: To differentiate between different types of modulation, a fast RSSI detector performs a RSSI measurement on a received signal. The output of the RSSI detector is sampled over a sampling window and generates sampled values. A processor calculates absolute values of piecewise first derivatives of the sampled values and sums the result to create a summation constant. A modulation detector determines the type of modulation based on the value of the summation constant and an RSSI compensation calculates a compensation factor to correct the RSSI measurement.

Abstract: To differentiate between different types of modulation, a fast RSSI detector performs a RSSI measurement on a received signal. The output of the RSSI detector is sampled over a sampling window and generates sampled values. A processor calculates absolute values of piecewise first derivatives of the sampled values and sums the result to create a summation constant. A modulation detector determines the type of modulation based on the value of the summation constant and an RSSI compensation calculates a compensation factor to correct the RSSI measurement.