Abstract: A voltage clamping circuit includes a current source having a fixed current source and a variable current source and a variable resistor receiving current from the current source. The variable resistor varies its resistance in response to an environmental operating condition. The voltage clamping circuit also includes an amplifier configured to compare a sensor node voltage with a reference voltage, the sensor node voltage being in communication with the voltage drop across the variable resistor. The amplifier is configured and connected to provide a control output to control the variable current source to modify current output from the variable current source to at least in part prevent the sensor node voltage from exceeding a reference voltage when certain operating conditions are present.

Abstract: A method and apparatus in a DC-feed controller for controlling a subscriber line interface circuit controlling voltage (alternately, current) on a telephone line comprising a pair of wires. A digital feedback signal is subtracted from a predetermined voltage (alternately, current) limit digital value to provide a digital error signal that represents the difference between the voltage (alternately, current) limit digital value and the digital feedback signal. The digital error signal is multiplied by a predetermined digital gain value to provide a scaled digital error value. The scaled digital error value is integrated over time to generate an integrated digital error signal having a first predetermined number n of significant bits.

Abstract: A technique is provided to linearize a MOS switch on-resistance and the nonlinear junction capacitance. The technique linearizes the sampling switch by using a buffer having substantially unity gain with proper DC shift to drive an isolated bulk terminal of the MOS well to improve the spurious free dynamic range (SFDR). In this way, the 2nd-order effect such as nonlinear body effect (VT(VSB)) and nonlinear junction capacitance (Cj(VSB)) can be substantially removed.

Abstract: A technique is provided to linearize a MOS switch on-resistance and the nonlinear junction capacitance. The technique linearizes the sampling switch by using a buffer having substantially unity gain with proper DC shift to drive an isolated bulk terminal of the MOS well to improve the spurious free dynamic range (SFDR). In this way, the 2nd-order effect such as nonlinear body effect (VT(VSB)) and nonlinear junction capacitance (Cj(VSB)) can be substantially removed.

Abstract: A method and apparatus in a DC-feed controller for controlling a subscriber line interface circuit controlling voltage (alternately, current) on a telephone line comprising a pair of wires. A digital feedback signal is subtracted from a predetermined voltage (alternately, current) limit digital value to provide a digital error signal that represents the difference between the voltage (alternately, current) limit digital value and the digital feedback signal. The digital error signal is multiplied by a predetermined digital gain value to provide a scaled digital error value. The scaled digital error value is integrated over time to generate an integrated digital error signal having a first predetermined number n of significant bits.