Abstract: In one embodiment, a method of preparing detectors for oxide bonding to an integrated chip, e.g., a readout integrated chip, includes providing a wafer having a plurality of detector elements with bumps thereon. A floating oxide layer is formed surrounding each of the bumps at a top portion thereof. An oxide-to-oxide bond is formed between the floating oxide layer and an oxide layer of the integrated chip which is provided in between corresponding bumps of the integrated chip. The oxide-to-oxide bond enables the bumps on the detector elements and the bumps on the integrated chip to be intimately contacted with each other, and removes essentially all mechanical stresses on and between the bumps. In another embodiment, a device has an interconnect interface that includes the oxide-to-oxide bond and an electrical connection between the bumps on the detector elements and the bumps on the integrated chip.

Abstract: In one embodiment, a method of preparing detectors for oxide bonding to an integrated chip, e.g., a readout integrated chip, includes providing a wafer having a plurality of detector elements with bumps thereon. A floating oxide layer is formed surrounding each of the bumps at a top portion thereof. An oxide-to-oxide bond is formed between the floating oxide layer and an oxide layer of the integrated chip which is provided in between corresponding bumps of the integrated chip. The oxide-to-oxide bond enables the bumps on the detector elements and the bumps on the integrated chip to be intimately contacted with each other, and removes essentially all mechanical stresses on and between the bumps. In another embodiment, a device has an interconnect interface that includes the oxide-to-oxide bond and an electrical connection between the bumps on the detector elements and the bumps on the integrated chip.

Abstract: A unit cell (20) is disclosed that has an input node for coupling to an output of a detector (D1) of electromagnetic radiation, such as IR or visible radiation. The unit cell includes a first capacitor (CintA) switchably coupled to the input node for receiving a charge signal from the detector, and for integrating the charge signal during a first integration period, as well as a second capacitor (CintB)switchably coupled to the input node for integrating the charge signal during a second integration period. The unit cell further includes an output multiplexer (32, 34) for selectively coupling the first capacitor and the second capacitor to an output signal line (38) during respective charge signal readout periods. In the preferred embodiment a duration of the first integration period is one of greater than or less than the second integration period, and the first integration period is one of non-overlapping or overlapping with the second integration period, and vice versa.

Abstract: The present invention concerns, in part, a method for fabricating a silicon PIN detector component wherein three handle wafers are bonded to the wafer at varying points in the fabrication process. The utilization of three handle wafers during fabrication significantly ease handling concerns associated with what would otherwise be a relatively thin and fragile wafer, providing a stable and strong base for supporting those portions of the wafer that will constitute the PIN detector component. In a variant of the present invention, the third handle wafer comprises an optical element transparent in the wavelength of interest.

Abstract: A low power delta-sigma analog to digital converter 10 for converting current mode signals without an amplifier includes an integration capacitor 26, a comparator 30, and a first switch 24 in parallel with one another and coupled to an integration node 28. A FET 20 and the first switch are disposed in series between a dump capacitor 25 and the integration node. A second switch 27 operates to discharge the dump capacitor, and an output of the comparator controls both switches in opposition. Preferably, no op-amps are included in the circuit, and current is supplied by an imaging component 5. In a first comparator state, the first capacitor charges, the first switch is open and the second switch is closed, and the dump capacitor discharges. In a comparator second state, the first switch is closed and the second switch is open, and the integration capacitor transfers a fixed amount of charge into the dump capacitor through an injection FET operating in saturation.

Abstract: A unit cell (20) is disclosed that has an input node for coupling to an output of a detector (D1) of electromagnetic radiation, such as IR or visible radiation. The unit cell includes a first capacitor (CintA) switchably coupled to the input node for receiving a charge signal from the detector, and for integrating the charge signal during a first integration period, as well as a second capacitor (CintB)switchably coupled to the input node for integrating the charge signal during a second integration period. The unit cell further includes an output multiplexer (32, 34) for selectively coupling the first capacitor and the second capacitor to an output signal line (38) during respective charge signal readout periods. In the preferred embodiment a duration of the first integration period is one of greater than or less than the second integration period, and the first integration period is one of non-overlapping or overlapping with the second integration period, and vice versa.

Abstract: The invention provides an automatic gain control system that is implemented by digital hardware. The digital hardware determines the range of a set of digital data values, and then examines each digital data value in a sequence. An index counter increments a sample count index i each time a new digital data value is examined and determines the absolute value of the ith digital data value. The digital hardware also counts both the number j of digital data values that exceed a high percentage value of the range, and the number k of digital data values that are less than a low percentage value of the range as the digital hardware runs through the sequence. If the digital hardware determines that a digital data value is greater than the high percentage value, the ratio j/i exceeds a first threshold value, and the gain level is not set to the lowest gain level, then the gain is decreased.

Abstract: A monolithic microelectronic array structure includes a microelectronic integrated circuit array having a first plurality of microelectronic integrated circuit elements each deposited on a front side of a substrate. The substrates are physically discontinuous so that each substrate comprises a substrate island which is physically separated from the other substrate islands. The monolithic microelectronic array structure optionally includes a first plurality of input/output elements with a respective input/output element associated with and directly connected to each of the microelectronic integrated circuit elements, and a second plurality of electrically conductive interconnects extending between the microelectronic integrated circuit elements of adjacent substrate islands. The monolithic microelectronic array structure may be planar, or it may be curved.

Abstract: A method for forming very large scale integrated circuit devices employs a reticle having plural discrete image fields which may be respectively blocked off and exposed to form patterns on an integrated circuit wafer substrate. The division of the circuit pattern to be imaged into separate image fields is based on repeatable horizontal, vertical and two dimensional structures in the overall circuit pattern of the integrated circuit. By repeatedly exposing image fields corresponding to repeatable structures, the size of the integrated circuit device may be scaled without requiring similar scaling of the reticle itself. Efficient exposure of an entire wafer may be provided by having image fields including circuit patterns which include the scribe lanes which separate the integrated circuits on the wafer to be imaged.

Abstract: This invention improves production yield and charge transfer speed and efficiency at the detector/register interface in a focal plane array and includes a novel meander channel CCD serial register in which charge packets generated in the array are stored. The electrode edge length across which charge is transferred at each entrance to the serial register is substantially increased in this invention in comparison with the prior art, resulting in a significant improvement in charge transfer efficiency and layout simplicity. Furthermore, this invention provides symmetrical surface potential distribution, and eliminates the gap instability in charge transfer.