Abstract: The present invention enables an enterprise to move from an implicitly trusted resource pool to an explicitly authenticated resource pool. Trust information is generally conveyed whenever a new resource is added to the pool and trust information is revoked when a resource is removed from the pool or is unable to provide its advertised resources. The dynamic, event driven conveyance of trust information is particularly important in highly virtualized environments where virtual resources are dynamically scaled up and down in response to resource demand.

Abstract: A method for modeling a circuit includes generating a circuit model based on a netlist that defines a plurality of connections between a plurality of circuit elements. The circuit model includes a model of one or more of the circuit elements. The method further includes determining a wire width associated with at least a selected connection based, at least in part, on design rules associated with the netlist. Additionally, the method includes determining a wire thickness associated with the selected connection based, at least in part, on a signal delay associated with the wire thickness. Furthermore, the method also includes routing the selected connection in the circuit model using a wire having a width substantially equal to the wire width calculated for the connection and a thickness equal to the wire thickness calculated for the connection and storing the circuit model in an electronic storage media.

Abstract: A circuit can include an amplifier having at least a first junction field effect transistor (JFET) of a first conductivity type with a source coupled to a first power supply node, and a drain coupled to an amplifier output node. A first variable bias circuit can be coupled between the drain and at least one gate of the first JFET. The first variable bias circuit can alter a direct current (DC) bias to the first JFET according a potential at the amplifier output node. A first bias impedance can be coupled between the drain of the first JFET and a second power supply node. The circuit can also include a non-linear transmission line (NLTL) coupled between the amplifier output and a gate of the first JFET. The NLTL being configured to propagate an electrical soliton.

Abstract: The present invention is directed to a distributed architecture of an information handling system, including a buried nucleus inaccessible for inspection without heroic means while the buried nucleus is in operation, and a trusted authority for generating a secure protocol. The secure protocol controls the operation of the buried nucleus.

Abstract: The present invention is directed to a distributed architecture of an information handling system, including a buried nucleus inaccessible for inspection without heroic means while the buried nucleus is in operation, and a trusted authority for generating a secure protocol. The secure protocol controls the operation of the buried nucleus.

Abstract: A method for modeling a circuit includes receiving a netlist that defines a plurality of connections between a plurality of circuit elements and identifying a subset of the connections. The method also includes routing the identified connections with a first group of wires having a first wire width and routing at least a portion of the remaining connections with a second wire width. The second wire width is smaller than the first wire width. The method further includes replacing the first group of wires with a third group of wires having the second wire width.

Abstract: A method for modeling a circuit includes generating a circuit model based on a netlist that defines a plurality of connections between a plurality of circuit elements. The circuit model includes a model of one or more of the circuit elements. The method further includes determining a wire width associated with at least a selected connection based, at least in part, on design rules associated with the netlist. Additionally, the method includes determining a wire thickness associated with the selected connection based, at least in part, on a signal delay associated with the wire thickness. Furthermore, the method also includes routing the selected connection in the circuit model using a wire having a width substantially equal to the wire width calculated for the connection and a thickness equal to the wire thickness calculated for the connection and storing the circuit model in an electronic storage media.

Abstract: A method for modeling a circuit includes receiving a netlist that defines a plurality of connections between a plurality of circuit elements and identifying a subset of the connections. The method also includes routing the identified connections with a first group of wires having a first wire width and routing at least a portion of the remaining connections with a second wire width. The second wire width is smaller than the first wire width. The method further includes replacing the first group of wires with a third group of wires having the second wire width.

Abstract: The present invention provides a comprehensive design environment defining a system architecture and methodology that may integrate interconnects, cores, ePLC, re-configurable processors and software into a manageable and predictable system designs that achieve on-time system IC design results meeting desired specifications and budgets. For example, an interscalable interconnect maybe provided that is scalable and isochronous capable. Additionally, an abstract language may be provided to be able to describe interconnecting core functions. Further, a self-programmable chip may be provided that, upon receiving a construct, it could program itself to achieve the desired functionality, such as through the use of on-chip knowledge and the like.

Abstract: A circuit can include an amplifier having at least a first junction field effect transistor (JFET) of a first conductivity type with a source coupled to a first power supply node, and a drain coupled to an amplifier output node. A first variable bias circuit can be coupled between the drain and at least one gate of the first JFET. The first variable bias circuit can alter a direct current (DC) bias to the first JFET according a potential at the amplifier output node. A first bias impedance can be coupled between the drain of the first JFET and a second power supply node. The circuit can also include a non-linear transmission line (NLTL) coupled between the amplifier output and a gate of the first JFET. The NLTL being configured to propagate an electrical soliton.

Abstract: The present invention pertains to a system and method for specifying links, connectivity and bandwidth in an interconnect fabric. For example, a method for allocating connectivity and bandwidth of an integrated circuit may include receiving an interconnect fabric description, the described interconnect fabric having a plurality of platforms linked over an isochronous interconnect fabric. An arrangement of links of the received interconnect fabric is virtualized based on bandwidth. An arrangement of links of the received interconnect fabric is virtualized based on connectivity. The links are allocated on the basis of the virtualized link arrangements based on bandwidth and connectivity.

Abstract: A secure disk drive is disclosed comprising a disk for storing data, and an input for receiving an encrypted message from a client disk drive, the encrypted message comprising ciphertext data and a client drive ID identifying the client disk drive. The secure disk drive comprises a secure drive key and an internal drive ID. A key generator within the secure disk drive generates a client drive key based on the client drive ID and the secure drive key, and an internal drive key based on the internal drive ID and the secure drive key. The secure disk drive further comprises an authenticator for verifying the authenticity of the encrypted message and generating an enable signal, the authenticator is responsive to the encrypted message and the client drive key. The secure disk drive further comprises a data processor comprising a message input for receiving the encrypted message from the client disk drive, and a data output for outputting the ciphertext data to be written to the disk.

Abstract: A computer network is disclosed comprising a plurality of interconnected network devices including a plurality of client computers, an authentication server computer operated by a system administrator, and a disk drive connected to the authentication server computer. The disk drive comprises an interface for receiving the personal authentication data and user access data from the system administrator, a disk for storing data, and a disk controller for controlling access to the disk. An authenticator within the disk drive, responsive to the personal authentication data, enables the disk controller, and cryptographic circuitry encrypts the user access data received from the system administrator into encrypted data stored on the disk.

Abstract: The present invention is directed to a timing abstraction and partitioning strategy for integrated circuit design. A method for designing an integrated circuit may include monitoring user interaction with logical blocks during a function design process of an integrated circuit. Indications of timing properties are derived during the functional design process.

Abstract: The present invention is directed to a method and system for optimally mapping a general set of resources to a specific integrated circuit design. In an exemplary aspect of the present invention, a method for optimally mapping a general set of resources to a specific integrated circuit design may include the following steps. Sets of transistors are first abstracted into abstracted resources. The abstracted resources may include a transformative resource, a coordinating resource, and a state management resource, and the like. Then, a sea-of-platforms is utilized for unifying a flexible and malleable collection of the abstracted resources in such a way as to optimize the abstracted resources for a specific integrated circuit design. Broken symmetry may be used to optimize the abstracted resources for the specific integrated circuit design. The broken symmetry may be in at least one of a physical 3-dimensional space, a temporal space and a code space.

Abstract: The present invention is directed to a method and apparatus for mapping platform-based design to multiple foundry processes. According to an exemplary aspect of the present invention, a method for mapping platform-based design to multiple foundry processes may include the following steps. First, a virtual process is defined to include at least one fabrication process. A virtual process is a totality of variables associated with the population of candidate processes and any other process of interest, which might be purely hypothetical, that would be capable, in principle, of accommodating some or all slices. A virtual process may or may not be realized and is an abstract logical container for a population of processes. Then, the virtual process may be stored into a database. The virtual process may be in a representation including a list of attributes of entities making up the fabrication process. Next, optimization of the database may be performed using mathematical and statistical tools.

Abstract: The present invention is directed to platform architecture used for integrated circuit design. A system for providing distributed dynamic functionality in an electronic environment may include a plurality of platforms. The platforms are suitable for providing a logic function, and include embedded programmable logic, memory and a reconfigurable core. The logic, memory and reconfigurable core are communicatively coupled via a fabric interconnect. A map is also included which expresses logic functions of the plurality of platforms.

Abstract: The present invention is directed to a method and apparatus for mapping platform-based design to multiple foundry processes. According to an exemplary aspect of the present invention, a predefined (or pre-specified) slice is successfully mapped on to a first fabrication process with a first set of design rules to produce a first result. Then the slice's ability to be mapped to a second fabrication process with a second set of design rules is evaluated to produce a second result. Next, the comparison between the two results is computed to produce a third result. The third result may be then used to modify the slice architecture, optimize the metalization process and/or modify the first or second fabrication process. The slice definition, the first set of design rules, the second set of design rules, the first result, the second result, and the third result may be stored into a database.

Abstract: The present invention is directed to a system and method for providing a collaborative integration of hybrid electronic and micro and sub-micro, including nano, level aggregates. A method of sampling aggregate nano behavior to determine progress by the nano aggregate toward a desired result may include sampling at least one of aggregate nano and aggregate micro behavior by a transducer. The aggregate behavior is measured through use of the sample by a macro level control apparatus. If the measured aggregate behavior is identified as diverging from progress toward a desired result, an effector is activated by the macro level control apparatus to influence the aggregate behavior toward progress toward the desired result.

Abstract: A disk drive is disclosed comprising a disk for storing data, the disk comprising a public area for storing plaintext data and a pristine area for storing encrypted data. The disk drive comprises a head for reading the encrypted data from the pristine area of the disk, and a control system for controlling access to the pristine area of the disk. Authentication circuitry within the disk drive is provided for authenticating a request received from an external entity to access the pristine area of the disk and for enabling the control system if the request is authenticated. The disk drive further comprises a secret drive key, and decryption circuitry responsive to the secret drive key, for decrypting the encrypted data stored in the pristine area of the disk.