Patents by Inventor Christopher L. Littler

Christopher L. Littler has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Three-dimensional ferroelectric integrated circuit having insulation layer between memory layers
    Patent number: 5487031
    Abstract: A ferroelectric integrated circuit is provided in which a first layer of conducting lines (14) is formed over an insulating base layer (10). A first ferroelectric layer (16) is formed overlying the first layer of conducting lines (14). A second layer of conducting lines (18) is formed overlying the first ferroelectric layer (16) with each of the conducting lines of the second layer of conducting lines (18) being substantially perpendicular to the conducting lines of the first layer of conducting lines (14). Potentials placed on selected conducting lines in the first and second layers of conducting lines (14 and 18) polarize areas of the first ferroelectric layer (16) between intersections of the selected conducting lines. Multiple layers may be stacked to form a three-dimensional ferroelectric integrated circuit.
    Type: Grant
    Filed: September 26, 1994
    Date of Patent: January 23, 1996
    Assignee: Texas Instruments Incorporated
    Inventors: Bruce E. Gnade, Russell F. Pinizzotto, Christopher L. Littler
  • Three-dimensional ferroelectric integrated circuit without insulation layer between memory layers
    Patent number: 5375085
    Abstract: A ferroelectric integrated circuit is provided in which a first layer of conducting lines (14) is formed over an insulating base layer (10). A first ferroelectric layer (16) is formed overlying the first layer of conducting lines (14). A second layer of conducting lines (18) is formed overlying the first ferroelectric layer (16) with each of the conducting lines of the second layer of conducting lines (18) being substantially perpendicular to the conducting lines of the first layer of conducting lines (14). Potentials placed on selected conducting lines in the first and second layers of conducting lines (14 and 18) polarize areas of the first ferroelectric layer (16) between intersections of the selected conducting lines. Multiple layers may be stacked to form a three-dimensional ferroelectric integrated circuit.
    Type: Grant
    Filed: September 30, 1992
    Date of Patent: December 20, 1994
    Assignee: Texas Instruments Incorporated
    Inventors: Bruce E. Gnade, Russell F. Pinizzotto, Christopher L. Littler