Patents by Inventor Christopher L. Rexer
Christopher L. Rexer has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 9595596Abstract: In one general aspect, a power device can include an active region having a plurality of pillars of a first conductivity type alternately arranged with a plurality of pillars of a second conductivity type. The power device can include a termination region surrounding at least a portion of the active region and can have a plurality of pillars of the first conductivity type alternately arranged with a plurality of pillars of the second conductivity type. Each of the plurality of pillars of the first conductivity type in the active region and the termination region can be defined by a trench. The power device can include an enrichment region at a bottom portion of one of the plurality of pillars of the first conductivity type in the active region.Type: GrantFiled: January 5, 2015Date of Patent: March 14, 2017Assignee: Fairchild Semiconductor CorporationInventors: Joseph A. Yedinak, Jaegil Lee, Chongman Yun, Praveen Muraleedharan Shenoy, Christopher L. Rexer
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Publication number: 20150187873Abstract: A power device includes an active region and a termination region surrounding the active region. A plurality of pillars of first and second conductivity type are alternately arranged in each of the active and termination regions. The pillars of first conductivity type in the active and termination regions have substantially the same width, and the pillars of second conductivity type in the active region have a smaller width than the pillars of second conductivity type in the termination region so that a charge balance condition in each of the active and termination regions results in a higher breakdown voltage in the termination region than in the active region.Type: ApplicationFiled: January 5, 2015Publication date: July 2, 2015Inventors: Joseph A. Yedinak, Jaegil Lee, Hocheol Jang, Chongman Yun, Praveen Muraleedharan Shenoy, Christopher L. Rexer, Changwook Kim, Jonghun Lee, Jasong M. Higgs, Dwayne S. Reichl, Joelle Sharp, Qi Wang, Yongsub Kim, Jungkil Lee, Mark L. Rinehimer, Jinyoung Jung
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Publication number: 20150069567Abstract: A power device includes a semiconductor region which in turn includes a plurality of alternately arranged pillars of first and second conductivity type. Each of the plurality of pillars of second conductivity type further includes a plurality of implant regions of the second conductivity type arranged on top of one another along the depth of pillars of second conductivity type, and a trench portion filled with semiconductor material of the second conductivity type directly above the plurality of implant regions of second conductivity type.Type: ApplicationFiled: September 19, 2014Publication date: March 12, 2015Inventors: Joseph A. Yedinak, Christopher L. Rexer, Mark L. Rinehimer, Praveen Muraleedharan Shenoy, Jaegil Lee, Hamza Yilmaz, Chongman Yun, Dwayne S. Reichl, James Pan, Rodney S. Ridley, Harold Heidenreich
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Patent number: 8928077Abstract: In one general aspect, a power device includes an active region having a plurality of pillars of a first conductivity type alternately arranged with a plurality of pillars of a second conductivity type where the plurality of pillars of the second conductivity type in the active region each have substantially the same width. The power device includes a termination region surrounding at least a portion of the active region and having a plurality of pillars of the first conductivity type alternately arranged with a plurality of pillars of the second conductivity type where the plurality of pillars of the second conductivity type in the active region each have substantially the same width and are smaller than each width of the pillars of the second conductivity type in the termination region. The power device includes a transition region disposed between the active region and the termination region.Type: GrantFiled: September 19, 2008Date of Patent: January 6, 2015Assignee: Fairchild Semiconductor CorporationInventors: JaeGil Lee, Chongman Yun, Hocheol Jang, Christopher L. Rexer, Praveen Muraleedharan Shenoy, Dwayne S. Reichl, Joseph A. Yedinak
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Patent number: 8786010Abstract: A power device includes a semiconductor region which in turn includes a plurality of alternately arranged pillars of first and second conductivity type. Each of the plurality of pillars of second conductivity type further includes a plurality of implant regions of the second conductivity type arranged on top of one another along the depth of pillars of second conductivity type, and a trench portion filled with semiconductor material of the second conductivity type directly above the plurality of implant regions of second conductivity type.Type: GrantFiled: April 27, 2011Date of Patent: July 22, 2014Assignee: Fairchild Semiconductor CorporationInventors: Joseph A. Yedinak, Christopher L. Rexer, Jaegil Lee, Hamza Yilmaz, Chongman Yun
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Patent number: 8502313Abstract: This document discusses, among other things, a semiconductor device including a first metal layer coupled to a source region and a second metal layer coupled to a gate structure, wherein at least a portion of the first and second metal layers overlap vertically.Type: GrantFiled: April 21, 2011Date of Patent: August 6, 2013Assignee: Fairchild Semiconductor CorporationInventors: Rohit Dikshit, Mark L. Rinehimer, Michael D. Gruenhagen, Joseph A. Yedinak, Tracie Petersen, Ritu Sodhi, Dan Kinzer, Christopher L. Rexer, Fred C. Session
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Patent number: 8362550Abstract: A semiconductor device includes a drift region, a well region extending above the drift region, an active trench including sidewalls and a bottom, the active trench extending through the well region and into the drift region and having at least portions of its sidewalls and bottom lined with dielectric material. The device further includes a shield disposed within the active trench and separated from the sidewalls of the active trench by the dielectric material, a gate disposed within the active trench above the first shield and separated therefrom by inter-electrode dielectric material, and source regions formed in the well region adjacent the active trench. The gate is separated from the sidewalls of the active trench by the dielectric material. The shield and the gate are made of materials having different work functions.Type: GrantFiled: June 13, 2011Date of Patent: January 29, 2013Assignee: Fairchild Semiconductor CorporationInventors: Christopher L. Rexer, Ritu Sodhi
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Patent number: 8357976Abstract: An electrical device on a single semiconductor substrate includes: an open base vertical PNP transistor placed in parallel with a wide bandgap, high voltage diode wherein the PNP transistor has a P doped collector region, an N-doped base layer, an N doped buffer layer, and a P doped emitter layer.Type: GrantFiled: December 21, 2010Date of Patent: January 22, 2013Assignee: Fairchild Semiconductor CorporationInventors: Joseph A. Yedinak, Richard L. Woodin, Christopher L. Rexer, Praveen Muralheedaran Shenoy, Kwanghoon Oh, Chongman Yun
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Publication number: 20120273916Abstract: A power device includes a semiconductor region which in turn includes a plurality of alternately arranged pillars of first and second conductivity type. Each of the plurality of pillars of second conductivity type further includes a plurality of implant regions of the second conductivity type arranged on top of one another along the depth of pillars of second conductivity type, and a trench portion filled with semiconductor material of the second conductivity type directly above the plurality of implant regions of second conductivity type.Type: ApplicationFiled: April 27, 2011Publication date: November 1, 2012Inventors: Joseph A. Yedinak, Christopher L. Rexer, Mark L. Rinehimer, Praveen Muraleedharan Shenoy, Jaegil Lee, Hamza Yilmaz, Chongman Yun, Dwayne S. Reichl, James Pan, Rodney S. Ridley, SR., Harold Heidenreich
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Publication number: 20120273884Abstract: A power device includes a semiconductor region which in turn includes a plurality of alternately arranged pillars of first and second conductivity type. Each of the plurality of pillars of second conductivity type further includes a plurality of implant regions of the second conductivity type arranged on top of one another along the depth of pillars of second conductivity type, and a trench portion filled with semiconductor material of the second conductivity type directly above the plurality of implant regions of second conductivity type.Type: ApplicationFiled: April 27, 2011Publication date: November 1, 2012Inventors: Joseph A. Yedinak, Christopher L. Rexer, Mark L. Rinehimer, Praveen Muraleedharan Shenoy, Jaegil Lee, Hamza Yilmaz, Chongman Yun, Dwayne S. Reichl, James Pan, Rodney S. Ridley, SR., Harold Heidenreich
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Publication number: 20120273871Abstract: A power device includes a semiconductor region which in turn includes a plurality of alternately arranged pillars of first and second conductivity type. Each of the plurality of pillars of second conductivity type further includes a plurality of implant regions of the second conductivity type arranged on top of one another along the depth of pillars of second conductivity type, and a trench portion filled with semiconductor material of the second conductivity type directly above the plurality of implant regions of second conductivity type.Type: ApplicationFiled: April 27, 2011Publication date: November 1, 2012Inventors: Joseph A. Yedinak, Christopher L. Rexer, Jaegil Lee, Hamza Yilmaz, Chongman Yun
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Publication number: 20120267714Abstract: This document discusses, among other things, a semiconductor device including a first metal layer coupled to a source region and a second metal layer coupled to a gate structure, wherein at least a portion of the first and second metal layers overlap vertically.Type: ApplicationFiled: April 21, 2011Publication date: October 25, 2012Inventors: Rohit Dikshit, Mark L. Rinehimer, Michael D. Gruenhagen, Joseph A. Yedinak, Tracie Petersen, Ritu Sodhi, Dan Kinzer, Christopher L. Rexer, Fred Session
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Publication number: 20120220091Abstract: A method for forming thick oxide at the bottom of a trench formed in a semiconductor substrate includes forming a conformal oxide film by a sub-atmospheric chemical vapor deposition process that fills the trench and covers a top surface of the substrate. The method also includes etching the oxide film off the top surface of the substrate and inside the trench to leave a substantially flat layer of oxide having a target thickness at the bottom of the trench.Type: ApplicationFiled: March 12, 2012Publication date: August 30, 2012Inventors: Ashok Challa, Alan Elbanhawy, Thomas E. Grebs, Nathan L. Kraft, Dean E. Probst, Rodney S. Ridley, Steven P. Sapp, Qi Wang, Chongman Yun, J.G. Lee, Peter H. Wilson, Joseph A. Yedinak, J.Y. Jung, H.C. Jang, Babak S. Sani, Richard Stokes, Gary M. Dolny, John Mytych, Becky Losee, Adam Selsley, Robert Herrick, James J. Murphy, Gordon K. Madson, Bruce D. Marchant, Christopher L. Rexer, Christopher B. Kocon, Debra S. Woolsey
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Publication number: 20120187474Abstract: A semiconductor device includes a drift region, a well region extending above the drift region, an active trench including sidewalls and a bottom, the active trench extending through the well region and into the drift region and having at least portions of its sidewalls and bottom lined with dielectric material. The device further includes a shield disposed within the active trench and separated from the sidewalls of the active trench by the dielectric material, a gate disposed within the active trench above the first shield and separated therefrom by inter-electrode dielectric material, and source regions formed in the well region adjacent the active trench. The gate is separated from the sidewalls of the active trench by the dielectric material. The shield and the gate are made of materials having different work functions.Type: ApplicationFiled: June 13, 2011Publication date: July 26, 2012Inventors: Christopher L. Rexer, Ritu Sodhi
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Patent number: 8124981Abstract: A wide bandgap silicon carbide device has an avalanche control structure formed in an epitaxial layer of a first conductivity type above a substrate that is connected to a first electrode of the device. A first region of a second conductivity type is in the upper surface of the epitaxial layer with a connection to a second electrode of the device. A second region of the first conductivity type lies below the first region and has a dopant concentration greater than the dopant concentration in the epitaxial layer.Type: GrantFiled: June 10, 2008Date of Patent: February 28, 2012Assignee: Fairchild Semiconductor CorporationInventors: Christopher L. Rexer, Gary M. Dolny, Richard L. Woodin, Carl Anthony Witt, Joseph Shovlin
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Patent number: 7859057Abstract: A method and device for protecting wide bandgap devices from failing during suppression of voltage transients. An improvement in avalanche capability is achieved by placing one or more diodes, or a PNP transistor, across the blocking junction of the wide bandgap device.Type: GrantFiled: August 6, 2009Date of Patent: December 28, 2010Assignee: Fairchild Semiconductor CorporationInventors: Joseph A. Yedinak, Richard L. Woodin, Christopher L. Rexer, Praveen Muralheedaran Shenoy, Kwanghoon Oh, Chongman Yun
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Publication number: 20090302327Abstract: A wide bandgap silicon carbide device has an avalanche control structure formed in an epitaxial layer of a first conductivity type above a substrate that is connected to a first electrode of the device. A first region of a second conductivity type is in the upper surface of the epitaxial layer with a connection to a second electrode of the device. A second region of the first conductivity type lies below the first region and has a dopant concentration greater than the dopant concentration in the epitaxial layer.Type: ApplicationFiled: June 10, 2008Publication date: December 10, 2009Inventors: Christopher L. Rexer, Gary M. Dolny, Richard L. Woodin, Carl Anthony Witt, Joseph Shovlin
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Publication number: 20080150020Abstract: A semiconductor power device includes a drift region of a first conductivity type, a well region extending above the drift region and having a second conductivity type opposite the first conductivity type, an active trench extending through the well region and into the drift region. The active trench, which includes sidewalls and bottom lined with dielectric material, is substantially filled with a first conductive layer and a second conductive layer. The second conductive layer forms a gate electrode and is disposed above the first conductive layer and is separated from the first conductive layer by an inter-electrode dielectric material. The device also includes source regions having the first conductivity type formed inside the well region and adjacent the active trench and a charge control trench that extends deeper into the drift region than the active trench and is substantially filled with material to allow for vertical charge control in the drift region.Type: ApplicationFiled: January 22, 2008Publication date: June 26, 2008Inventors: Ashok Challa, Alan Elbanhawy, Thomas E. Grebs, Nathan L. Kraft, Dean E. Probst, Rodney S. Ridley, Steven P. Sapp, Qi Wang, Chongman Yun, J. G. Lee, Peter H. Wilson, Joseph A. Yedinak, J. Y. Jung, H. C. Jang, Babak S. Sani, Richard Stokes, Gary M. Dolny, John Mytych, Becky Losee, Adam Selsley, Robert Herrick, James J. Murphy, Gordon K. Madson, Bruce D. Marchant, Christopher L. Rexer, Christopher B. Kocon, Debra S. Woolsey
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Publication number: 20080135931Abstract: A semiconductor power device includes a drift region of a first conductivity type, a well region extending above the drift region and having a second conductivity type opposite the first conductivity type, an active trench extending through the well region and into the drift region, source regions having the first conductivity type formed in the well region adjacent the active trench, and a first termination trench extending below the well region and disposed at an outer edge of an active region of the device. The sidewalls and bottom of the active trench are lined with dielectric material, and substantially filled with a first conductive layer forming an upper electrode and a second conductive layer forming a lower electrode, the upper electrode being disposed above the lower electrode and separated therefrom by inter-electrode dielectric material.Type: ApplicationFiled: February 15, 2008Publication date: June 12, 2008Inventors: Ashok Challa, Alan Elbanhawy, Thomas E. Grebs, Nathan L. Kraft, Dean E. Probst, Rodney S. Ridlay, Steven P. Sapp, Qi Wang, Chongman Yun, J.G. Lee, Peter H. Wilson, Joseph A. Yedinak, J.Y. Jung, H.C. Jang, Babak S. Sanl, Richard Stokes, Gary M. Dolny, John Mytych, Becky Losee, Adam Selsley, Robert Herrick, James J. Murphy, Gordon K. Madson, Bruce D. Marchant, Christopher L. Rexer, Christopher B. Kocon, Debra S. Woolsey
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Patent number: 5940689Abstract: A method of fabricating a UMOS semiconductor device includes a blanket implant of an N type dopant into a surface of a substrate (for forming source regions), a high energy implant of a P type dopant into the substrate (for forming body regions), an etch through a hard mask to form trenches and mesas (each of the mesas having a source region at its top and a body region below), and concurrently (i) providing a gate dielectric on the sidewalls of the trenches and (ii) redistributing the dopants so that the body regions extend deeper into the substrate beneath the centers of the mesas than adjacent the walls of the trenches. Contact windows are etched in the mesas to allow electrical contact with the source regions and the body regions. The initial implant of P type dopant may be a blanket implant or an implant through a mask which concentrates the P type dopant in the centers of the mesas.Type: GrantFiled: June 30, 1997Date of Patent: August 17, 1999Assignee: Harris CorporationInventors: Christopher L. Rexer, Mark L. Rineheimer, John M. S. Neilson, Thomas E. Grebs