Abstract: A multi-port memory device comprising a memory cell coupled to a first port and a second port. The second port receives write data for writing into the memory cell. The multi-port memory device further comprises an undo circuit coupled to the memory cell. The undo circuit invalidates the write data in response to receiving a busy signal. When the undo circuit invalidates the write data, the write data is not written into the memory cell. The busy signal indicates that the first port is enabled to access the memory cell at substantially the same time that the second port receives the write data. The busy signal may be generated by arbitration circuitry in the multi-port memory device or by arbitration circuitry in another device coupled to the multi-port memory device. For one embodiment, the busy signal may be generated by arbitration circuitry in a second multi-port memory device coupled in width expansion with the first multi-port memory device.