Abstract: Techniques and mechanisms for a power management circuit to monitor a power domain during one or more attempts to configure a low power state of the power domain. In an embodiment, the one or more attempts are performed during an instance of a local power state at a processor that is coupled to the power management circuit. The monitoring is to detect for a condition wherein the power domain has been in a power state, other than the low power state, for longer than a predetermined threshold length of time. Where the condition is detected, the power management circuit generates one or more signals which change the local power state of the processor, or interrupt an operating system that is executed with the processor. In another embodiment, the power management circuit provides analytic data based on the monitoring of the one or more attempts.

Abstract: Techniques and mechanisms for a power management circuit to monitor a power domain during one or more attempts to configure a low power state of the power domain. In an embodiment, the one or more attempts are performed during an instance of a local power state at a processor that is coupled to the power management circuit. The monitoring is to detect for a condition wherein the power domain has been in a power state, other than the low power state, for longer than a predetermined threshold length of time. Where the condition is detected, the power management circuit generates one or more signals which change the local power state of the processor, or interrupt an operating system that is executed with the processor. In another embodiment, the power management circuit provides analytic data based on the monitoring of the one or more attempts.

Abstract: One embodiment includes hardware logic to: receive first and second communications corresponding to an intellectual property (IP) core and begin a timed session in response to receiving the second communication; determine the firmware has completed processing the second communication before expiration of the timed session and increase a latency state corresponding to a resource in response to determining the firmware has completed processing the second communication before expiration of the timed session; receive a third communication corresponding to the IP core and begin an additional timed session in response to receiving the third communication; determine the firmware failed to complete processing the third communication before expiration of the additional timed session and decrease the latency state corresponding to the resource in response to determining the firmware failed to complete processing the third communication before expiration of the additional timed session.

Abstract: One embodiment includes hardware logic to: receive first and second communications corresponding to an intellectual property (IP) core and begin a timed session in response to receiving the second communication; determine the firmware has completed processing the second communication before expiration of the timed session and increase a latency state corresponding to a resource in response to determining the firmware has completed processing the second communication before expiration of the timed session; receive a third communication corresponding to the IP core and begin an additional timed session in response to receiving the third communication; determine the firmware failed to complete processing the third communication before expiration of the additional timed session and decrease the latency state corresponding to the resource in response to determining the firmware failed to complete processing the third communication before expiration of the additional timed session.

Abstract: A power button override allows a persistent memory enabled platform to preserve data in persistent memory before initiating shutdown in a manner that is transparent to the user. The power button override prevents shutdown until all of the volatile cache and any other data in the platform has been flushed to persistent memory.

Abstract: A power button override allows a persistent memory enabled platform to preserve data in persistent memory before initiating shutdown in a manner that is transparent to the user. The power button override prevents shutdown until all of the volatile cache and any other data in the platform has been flushed to persistent memory.

Abstract: An automated system for testing a variety of transmissions and drive line gearbox components, and more particularly helicopter transmissions, for reliability, life expectancy, efficiency, and the like on a semi-automated basis. The system powers a unit under test with a pair of AC, variable speed drive motors connected to the transmission through relatively low speed gearboxes which in turn drive the input(s) of the test unit through geared cartridge spindles (GCSs) employing planetary gearset inputs driving a higher speed machine tool type spindle with an output chuck system which can automatically couple to adapters preloaded on the unit under test. Similar GCSs couple the outputs of the test unit to AC motors which act as generators to power the driving motors and thereby reduce the required electric power input to the losses in the system.

Abstract: An automated system for testing a variety of transmissions and drive line gearbox components, and more particularly helicopter transmissions, for reliability, life expectancy, efficiency, and the like on a semi-automated basis. The system powers a unit under test with a pair of AC, variable speed drive motors connected to the transmission through relatively low speed gearboxes which in turn drive the input(s) of the test unit through geared cartridge spindles (GCSs) employing planetary gearset inputs driving a higher speed machine tool type spindle with an output chuck system which can automatically couple to adapters preloaded on the unit under test. Similar GCSs couple the outputs of the test unit to AC motors which act as generators to power the driving motors and thereby reduce the required electric power input to the losses in the system.

Abstract: A configuration memory space is scanned to locate an identification register whose value matches a predetermined value. The identification register identifies the location of a structure within the configuration space. The location of the beginning of the structure is used along with a predetermined (known) offset to determine the address of a desired configuration register.