Abstract: A digital-to-analog converter (DAC) including a DAC core circuit having a plurality of input lines each being responsive to a digital bit input signal and an output line outputting a converted analog signal of the digital bits. The DAC also includes a clock circuit responsive to a clock input signal at one frequency and outputting a clock output signal at another frequency. The DAC also includes a clock tree distribution network responsive to the clock output signal from the clock circuit and splitting the clock output signal into a plurality of split clock signals that are applied to the DAC core circuit, where the DAC core circuit is fabricated in an indium phosphide (InP) semiconductor material and the clock tree distribution network is fabricated in a silicon germanium (SiGe) semiconductor material.

Abstract: A digital-to-analog converter (DAC) including a DAC core circuit having a plurality of input lines each being responsive to a digital bit input signal and an output line outputting a converted analog signal of the digital bits. The DAC also includes a clock circuit responsive to a clock input signal at one frequency and outputting a clock output signal at another frequency. The DAC also includes a clock tree distribution network responsive to the clock output signal from the clock circuit and splitting the clock output signal into a plurality of split clock signals that are applied to the DAC core circuit, where the DAC core circuit is fabricated in an indium phosphide (InP) semiconductor material and the clock tree distribution network is fabricated in a silicon germanium (SiGe) semiconductor material.

Abstract: A subtraction circuit. The novel subtraction circuit includes a first circuit for providing an impedance between an input node and an output node, a second circuit for generating a first current and applying the first current to the output node to produce a desired voltage drop between the input and output nodes, and a third circuit for independently generating a second current relative to the first current and applying the second current to the input node to regulate a current input to the first circuit at the input node. The second and third circuits are implemented using two digital to analog converters (DACs), a precision DAC for generating the first current and a non-trimmed “dummy” DAC for generating the second current. In an illustrative embodiment, the subtraction circuit is used in the reconstruction stage of a subranging analog to digital converter.

Abstract: A clamped comparator. The novel comparator includes a first circuit for comparing first and second input signals and generating a digital output, and a second circuit for receiving a control signal and in accordance therewith decoupling the input signals from the output. The second circuit includes one or more switching circuits adapted to clamp the signal path between the input signals and the output when the circuit is operating in a ‘mute’ mode. In an illustrative embodiment, the comparator also includes a pre-amplifier with an amplifier stage, and the switching circuit is adapted to turn off the amplifier stage and/or steer the outputs of the amplifier stage out of the signal path, when the circuit is in the ‘mute’ mode.

Abstract: A DAC (10) including an operational amplifier (12) having an input terminal; a plurality of current paths coupled to the input terminal; a plurality of current sources (I1/2-I4/2); and an arrangement (11) for switchably coupling current from at least two of the cells to a respective one of the paths in response to an input signal. In a specific embodiment, the inventive DAC (10) further includes a first resistive element (2R1-2R4) disposed in each of the current paths, a second resistive element (R1-R4) disposed between the current paths, and a feedback resistor (RF) disposed between an output terminal of the amplifier and the input terminal thereof. In the illustrative embodiment, the coupling arrangement includes a plurality of switches (SW1-SW4); each of the switches is adapted to switch half of the current from a first source and half of the current from a second source into a respective one of the paths.