Abstract: A system can include an analyzer module configured to analyze spill code generated by a register allocator to determine that register spill instructions can be paired, wherein paired register spill instructions relate to corresponding register locations in each of a first register set and a second register set and that no instructions between said register spill instructions modify any of said register spill instructions; a rewriter module configured to, based on the determining, modify said register spill instructions as a parallel register spill instruction; and a storage module configured to configure storage of associated register spills in memory so said register spills can be loaded back in parallel into corresponding registers of said first and second register sets based on said modified parallel register spill instruction, wherein the configuration of storage includes allocation of space on a memory stack such that the register spills are double word aligned.

Abstract: A system can include an analyzer module configured to analyze spill code generated by a register allocator to determine that register spill instructions can be paired, wherein paired register spill instructions relate to corresponding register locations in each of a first register set and a second register set and that no instructions between said register spill instructions modify any of said register spill instructions; a rewriter module configured to, based on the determining, modify said register spill instructions as a parallel register spill instruction; and a storage module configured to configure storage of associated register spills in memory so said register spills can be loaded back in parallel into corresponding registers of said first and second register sets based on said modified parallel register spill instruction, wherein the configuration of storage includes allocation of space on a memory stack such that the register spills are double word aligned.

Abstract: Embodiments of the present invention provide a design for handling register overflow in a CPU having parallel registers. In an embodiment, spill code generated by a registers allocator may be analyzed to identify register spill instructions that can be associated. Register spill instructions that can be associated may be rewritten as parallel spill instructions, and the corresponding register spills may be configured for storage into memory in a manner permitting them to be loaded back to the registers in parallel.

Abstract: The present invention provides a design for handling register overflow in a parallel register architecture. In an embodiment, spill code generated by a register allocator may be analyzed to identify register spill instructions that can be associated. Register spill instructions that can be associated may be rewritten as parallel spill instructions, and the corresponding register spills may be configured for storage into memory in a manner permitting them to be loaded back to the registers in parallel.