Patents by Inventor Christopher Larsen

Christopher Larsen has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20240324223
    Abstract: Some embodiments include an integrated assembly having a first deck. The first deck has first memory cell levels alternating with first insulative levels. A second deck is over the first deck. The second deck has second memory cell levels alternating with second insulative levels. A cell-material-pillar passes through the first and second decks. Memory cells are along the first and second memory cell levels and include regions of the cell-material-pillar. An intermediate level is between the first and second decks. The intermediate level includes a buffer region adjacent the cell-material-pillar. The buffer region includes a composition different from the first and second insulative materials, and different from the first and second conductive regions. Some embodiments include methods of forming integrated assemblies.
    Type: Application
    Filed: June 3, 2024
    Publication date: September 26, 2024
    Inventors: S. M. Istiaque Hossain, Prakash Rau Mokhna Rau, Arun Kumar Dhayalan, Damir Fazil, Joel D. Peterson, Anilkumar Chandolu, Albert Fayrushin, George Matamis, Christopher Larsen, Rokibul Islam
  • Patent number: 12004351
    Abstract: Some embodiments include an integrated assembly having a first deck. The first deck has first memory cell levels alternating with first insulative levels. A second deck is over the first deck. The second deck has second memory cell levels alternating with second insulative levels. A cell-material-pillar passes through the first and second decks. Memory cells are along the first and second memory cell levels and include regions of the cell-material-pillar. An intermediate level is between the first and second decks. The intermediate level includes a buffer region adjacent the cell-material-pillar. The buffer region includes a composition different from the first and second insulative materials, and different from the first and second conductive regions. Some embodiments include methods of forming integrated assemblies.
    Type: Grant
    Filed: July 20, 2022
    Date of Patent: June 4, 2024
    Inventors: S. M. Istiaque Hossain, Prakash Rau Mokhna Rau, Arun Kumar Dhayalan, Damir Fazil, Joel D. Peterson, Anilkumar Chandolu, Albert Fayrushin, George Matamis, Christopher Larsen, Rokibul Islam
  • Publication number: 20230209824
    Abstract: Memory circuitry comprising strings of memory cells comprises laterally-spaced memory blocks individually comprising a vertical stack comprising alternating insulative tiers and conductive tiers. Channel-material strings of memory cells extend through the insulative tiers and the conductive tiers in a memory-array region. The insulative tiers and the conductive tiers of the laterally-spaced memory blocks extend from the memory-array region into a stair-step region. Individual stairs in the stair-step region comprise one of the conductive tiers. Conductive vias are individually directly against conducting material that is in the one conductive tier in one of the individual stairs. Insulator material in the stair-step region is directly above the stairs. An insulative-material lining is circumferentially around and extends elevationally along individual of the conductive vias between the individual conductive vias and the insulator material.
    Type: Application
    Filed: January 14, 2022
    Publication date: June 29, 2023
    Applicant: Micron Technology, Inc.
    Inventors: Shuangqiang Luo, Christopher Larsen, Rui Zhang
  • Patent number: 11600494
    Abstract: A method used in forming an array of elevationally-extending strings of memory cells comprises forming a stack comprising vertically-alternating insulative tiers and wordline tiers. The stack comprises an etch-stop tier between a first tier and a second tier of the stack. The etch-stop tier is of different composition from those of the insulative tiers and the wordline tiers. Etching is conducted into the insulative tiers and the wordline tiers that are above the etch-stop tier to the etch-stop tier to form channel openings that have individual bases comprising the etch-stop tier. The etch-stop tier is penetrated through to extend individual of the channel openings there-through. After extending the individual channel openings through the etch-stop tier, etching is conducted into and through the insulative tiers and the wordline tiers that are below the etch-stop tier to extend the individual channel openings deeper into the stack below the etch-stop tier.
    Type: Grant
    Filed: May 12, 2021
    Date of Patent: March 7, 2023
    Assignee: Micron Technology, Inc.
    Inventors: John D. Hopkins, Gordon A. Haller, Tom J. John, Anish A. Khandekar, Christopher Larsen, Kunal Shrotri
  • Publication number: 20220367512
    Abstract: Some embodiments include an integrated assembly having a first deck. The first deck has first memory cell levels alternating with first insulative levels. A second deck is over the first deck. The second deck has second memory cell levels alternating with second insulative levels. A cell-material-pillar passes through the first and second decks. Memory cells are along the first and second memory cell levels and include regions of the cell-material-pillar. An intermediate level is between the first and second decks. The intermediate level includes a buffer region adjacent the cell-material-pillar. The buffer region includes a composition different from the first and second insulative materials, and different from the first and second conductive regions. Some embodiments include methods of forming integrated assemblies.
    Type: Application
    Filed: July 20, 2022
    Publication date: November 17, 2022
    Applicant: Micron Technology, Inc.
    Inventors: S.M. Istiaque Hossain, Prakash Rau Mokhna Rau, Arun Kumar Dhayalan, Damir Fazil, Joel D. Peterson, Anilkumar Chandolu, Albert Fayrushin, George Matamis, Christopher Larsen, Rokibul Islam
  • Patent number: 11430809
    Abstract: Some embodiments include an integrated assembly having a first deck. The first deck has first memory cell levels alternating with first insulative levels. A second deck is over the first deck. The second deck has second memory cell levels alternating with second insulative levels. A cell-material-pillar passes through the first and second decks. Memory cells are along the first and second memory cell levels and include regions of the cell-material-pillar. An intermediate level is between the first and second decks. The intermediate level includes a buffer region adjacent the cell-material-pillar. The buffer region includes a composition different from the first and second insulative materials, and different from the first and second conductive regions. Some embodiments include methods of forming integrated assemblies.
    Type: Grant
    Filed: August 4, 2020
    Date of Patent: August 30, 2022
    Assignee: Micron Technology, Inc.
    Inventors: S. M. Istiaque Hossain, Prakash Rau Mokhna Rau, Arun Kumar Dhayalan, Damir Fazil, Joel D. Peterson, Anilkumar Chandolu, Albert Fayrushin, George Matamis, Christopher Larsen, Rokibul Islam
  • Publication number: 20220045086
    Abstract: Some embodiments include an integrated assembly having a first deck. The first deck has first memory cell levels alternating with first insulative levels. A second deck is over the first deck. The second deck has second memory cell levels alternating with second insulative levels. A cell-material-pillar passes through the first and second decks. Memory cells are along the first and second memory cell levels and include regions of the cell-material-pillar. An intermediate level is between the first and second decks. The intermediate level includes a buffer region adjacent the cell-material-pillar. The buffer region includes a composition different from the first and second insulative materials, and different from the first and second conductive regions. Some embodiments include methods of forming integrated assemblies.
    Type: Application
    Filed: August 4, 2020
    Publication date: February 10, 2022
    Applicant: Micron Technology, Inc.
    Inventors: S.M. Istiaque Hossain, Prakash Rau Mokhna Rau, Arun Kumar Dhayalan, Damir Fazil, Joel D. Peterson, Anilkumar Chandolu, Albert Fayrushin, George Matamis, Christopher Larsen, Rokibul Islam
  • Publication number: 20210265171
    Abstract: A method used in forming an array of elevationally-extending strings of memory cells comprises forming a stack comprising vertically-alternating insulative tiers and wordline tiers. The stack comprises an etch-stop tier between a first tier and a second tier of the stack. The etch-stop tier is of different composition from those of the insulative tiers and the wordline tiers. Etching is conducted into the insulative tiers and the wordline tiers that are above the etch-stop tier to the etch-stop tier to form channel openings that have individual bases comprising the etch-stop tier. The etch-stop tier is penetrated through to extend individual of the channel openings there-through. After extending the individual channel openings through the etch-stop tier, etching is conducted into and through the insulative tiers and the wordline tiers that are below the etch-stop tier to extend the individual channel openings deeper into the stack below the etch-stop tier.
    Type: Application
    Filed: May 12, 2021
    Publication date: August 26, 2021
    Applicant: Micron Technology, Inc.
    Inventors: John D. Hopkins, Gordon A. Haller, Tom J. John, Anish A. Khandekar, Christopher Larsen, Kunal Shrotri
  • Patent number: 11101280
    Abstract: A method used in forming a memory array comprising strings of memory cells comprises forming a stack comprising vertically-alternating first tiers and second tiers comprising memory-block regions having channel-material strings therein. Conductor-material contacts are directly against the channel material of individual of the channel-material strings. First insulator material is formed directly above the conductor-material contacts. The first insulator material comprises at least one of (a) and (b), where (a): silicon, nitrogen, and one or more of carbon, oxygen, boron, and phosphorus, and (b): silicon carbide. Second insulator material is formed directly above the first insulator material and the conductor-material contacts. The second insulator material is devoid of each of the (a) and (b). Third insulator material is formed directly above the second insulator material, the first insulator material, and the conductor-material contacts. The third insulator material comprises at least one of the (a) and (b).
    Type: Grant
    Filed: December 27, 2019
    Date of Patent: August 24, 2021
    Assignee: Micron Technology, Inc.
    Inventors: Anilkumar Chandolu, S.M. Istiaque Hossain, Darwin A. Clampitt, Arun Kumar Dhayalan, Kevin R. Gast, Christopher Larsen, Prakash Rau Mokhna Rau, Shashank Saraf
  • Publication number: 20210202515
    Abstract: A method used in forming a memory array comprising strings of memory cells comprises forming a stack comprising vertically-alternating first tiers and second tiers comprising memory-block regions having channel-material strings therein. Conductor-material contacts are directly against the channel material of individual of the channel-material strings. First insulator material is formed directly above the conductor-material contacts. The first insulator material comprises at least one of (a) and (b), where (a): silicon, nitrogen, and one or more of carbon, oxygen, boron, and phosphorus, and (b): silicon carbide. Second insulator material is formed directly above the first insulator material and the conductor-material contacts. The second insulator material is devoid of each of the (a) and (b). Third insulator material is formed directly above the second insulator material, the first insulator material, and the conductor-material contacts. The third insulator material comprises at least one of the (a) and (b).
    Type: Application
    Filed: December 27, 2019
    Publication date: July 1, 2021
    Applicant: Micron Technology, Inc.
    Inventors: Anilkumar Chandolu, S.M. Istiaque Hossain, Darwin A. Clampitt, Arun Kumar Dhayalan, Kevin R. Gast, Christopher Larsen, Prakash Rau Mokhna Rau, Shashank Saraf
  • Patent number: 11037797
    Abstract: A method used in forming an array of elevationally-extending strings of memory cells comprises forming a stack comprising vertically-alternating insulative tiers and wordline tiers. The stack comprises an etch-stop tier between a first tier and a second tier of the stack. The etch-stop tier is of different composition from those of the insulative tiers and the wordline tiers. Etching is conducted into the insulative tiers and the wordline tiers that are above the etch-stop tier to the etch-stop tier to form channel openings that have individual bases comprising the etch-stop tier. The etch-stop tier is penetrated through to extend individual of the channel openings there-through. After extending the individual channel openings through the etch-stop tier, etching is conducted into and through the insulative tiers and the wordline tiers that are below the etch-stop tier to extend the individual channel openings deeper into the stack below the etch-stop tier.
    Type: Grant
    Filed: April 21, 2020
    Date of Patent: June 15, 2021
    Assignee: Micron Technology, Inc.
    Inventors: John D. Hopkins, Gordon A. Haller, Tom J. John, Anish A. Khandekar, Christopher Larsen, Kunal Shrotri
  • Publication number: 20200251347
    Abstract: A method used in forming an array of elevationally-extending strings of memory cells comprises forming a stack comprising vertically-alternating insulative tiers and wordline tiers. The stack comprises an etch-stop tier between a first tier and a second tier of the stack. The etch-stop tier is of different composition from those of the insulative tiers and the wordline tiers. Etching is conducted into the insulative tiers and the wordline tiers that are above the etch-stop tier to the etch-stop tier to form channel openings that have individual bases comprising the etch-stop tier. The etch-stop tier is penetrated through to extend individual of the channel openings there-through. After extending the individual channel openings through the etch-stop tier, etching is conducted into and through the insulative tiers and the wordline tiers that are below the etch-stop tier to extend the individual channel openings deeper into the stack below the etch-stop tier.
    Type: Application
    Filed: April 21, 2020
    Publication date: August 6, 2020
    Applicant: Micron Technology, Inc.
    Inventors: John D. Hopkins, Gordon A. Haller, Tom J. John, Anish A. Khandekar, Christopher Larsen, Kunal Shrotri
  • Patent number: 10702295
    Abstract: A device for dilating an ostium of a paranasal sinus of a human or animal subject may include: a handle; an elongate shaft having a proximal end coupled with the handle and extending to a distal end; a guidewire disposed through at least a portion of the shaft lumen; a dilator having a non-expanded configuration and an expanded configuration; and a slide member coupled with at least one of the guidewire or the dilator through the longitudinal opening of the shaft for advancing the guidewire and/or the dilator relative to the shaft.
    Type: Grant
    Filed: November 16, 2017
    Date of Patent: July 7, 2020
    Assignee: Acclarent, Inc.
    Inventors: Thomas R. Jenkins, Eric Goldfarb, Tom Thanh Vo, Joshua Makower, Robert N. Wood, Ronda M. Heiser, Christopher Larsen, Daniel T. Harfe
  • Patent number: 10665469
    Abstract: A method used in forming an array of elevationally-extending strings of memory cells comprises forming a stack comprising vertically-alternating insulative tiers and wordline tiers. The stack comprises an etch-stop tier between a first tier and a second tier of the stack. The etch-stop tier is of different composition from those of the insulative tiers and the wordline tiers. Etching is conducted into the insulative tiers and the wordline tiers that are above the etch-stop tier to the etch-stop tier to form channel openings that have individual bases comprising the etch-stop tier. The etch-stop tier is penetrated through to extend individual of the channel openings there-through. After extending the individual channel openings through the etch-stop tier, etching is conducted into and through the insulative tiers and the wordline tiers that are below the etch-stop tier to extend the individual channel openings deeper into the stack below the etch-stop tier.
    Type: Grant
    Filed: September 11, 2018
    Date of Patent: May 26, 2020
    Assignee: Micron Technology, Inc.
    Inventors: John D. Hopkins, Gordon A. Haller, Tom J. John, Anish A. Khandekar, Christopher Larsen, Kunal Shrotri
  • Patent number: 10658382
    Abstract: An elevationally-extending string of memory cells comprises an upper stack elevationally over a lower stack. The upper and lower stacks individually comprise vertically-alternating tiers comprising control gate material of individual charge storage field effect transistors vertically alternating with insulating material. An upper stack channel pillar extends through multiple of the vertically-alternating tiers in the upper stack and a lower stack channel pillar extends through multiple of the vertically-alternating tiers in the lower stack. Tunnel insulator, charge storage material, and control gate blocking insulator is laterally between the respective upper and lower stack channel pillars and the control gate material. A conductive interconnect comprising conductively-doped semiconductor material is elevationally between and electrically couples the upper and lower stack channel pillars together. The conductively-doped semiconductor material comprises a first conductivity-producing dopant.
    Type: Grant
    Filed: April 17, 2019
    Date of Patent: May 19, 2020
    Assignee: Micron Technology, Inc.
    Inventors: John D. Hopkins, David Daycock, Yushi Hu, Christopher Larsen, Dimitrios Pavlopoulos
  • Publication number: 20200083059
    Abstract: A method used in forming an array of elevationally-extending strings of memory cells comprises forming a stack comprising vertically-alternating insulative tiers and wordline tiers. The stack comprises an etch-stop tier between a first tier and a second tier of the stack. The etch-stop tier is of different composition from those of the insulative tiers and the wordline tiers. Etching is conducted into the insulative tiers and the wordline tiers that are above the etch-stop tier to the etch-stop tier to form channel openings that have individual bases comprising the etch-stop tier. The etch-stop tier is penetrated through to extend individual of the channel openings there-through. After extending the individual channel openings through the etch-stop tier, etching is conducted into and through the insulative tiers and the wordline tiers that are below the etch-stop tier to extend the individual channel openings deeper into the stack below the etch-stop tier.
    Type: Application
    Filed: September 11, 2018
    Publication date: March 12, 2020
    Applicant: Micron Technology, Inc.
    Inventors: John D. Hopkins, Gordon A. Haller, Tom J. John, Anish A. Khandekar, Christopher Larsen, Kunal Shrotri
  • Patent number: 10541252
    Abstract: Some embodiments include a memory array which has a vertical stack of alternating insulative levels and wordline levels. The wordline levels have terminal ends corresponding to control gate regions. Charge-trapping material is along the control gate regions of the wordline levels and not along the insulative levels. The charge-trapping material is spaced from the control gate regions by charge-blocking material. Channel material extends vertically along the stack and is laterally spaced from the charge-trapping material by dielectric material. Some embodiments include methods of forming NAND memory arrays.
    Type: Grant
    Filed: May 13, 2019
    Date of Patent: January 21, 2020
    Assignee: Micron Technology, Inc.
    Inventors: David Daycock, Richard J. Hill, Christopher Larsen, Woohee Kim, Justin B. Dorhout, Brett D. Lowe, John D. Hopkins, Qian Tao, Barbara L. Casey
  • Publication number: 20190267396
    Abstract: Some embodiments include a memory array which has a vertical stack of alternating insulative levels and wordline levels. The wordline levels have terminal ends corresponding to control gate regions. Charge-trapping material is along the control gate regions of the wordline levels and not along the insulative levels. The charge-trapping material is spaced from the control gate regions by charge-blocking material. Channel material extends vertically along the stack and is laterally spaced from the charge-trapping material by dielectric material. Some embodiments include methods of forming NAND memory arrays.
    Type: Application
    Filed: May 13, 2019
    Publication date: August 29, 2019
    Applicant: Micron Technology, Inc.
    Inventors: David Daycock, Richard J. Hill, Christopher Larsen, Woohee Kim, Justin B. Dorhout, Brett D. Lowe, John D. Hopkins, Qian Tao, Barbara L. Casey
  • Publication number: 20190244972
    Abstract: An elevationally-extending string of memory cells comprises an upper stack elevationally over a lower stack. The upper and lower stacks individually comprise vertically-alternating tiers comprising control gate material of individual charge storage field effect transistors vertically alternating with insulating material. An upper stack channel pillar extends through multiple of the vertically-alternating tiers in the upper stack and a lower stack channel pillar extends through multiple of the vertically-alternating tiers in the lower stack. Tunnel insulator, charge storage material, and control gate blocking insulator is laterally between the respective upper and lower stack channel pillars and the control gate material. A conductive interconnect comprising conductively-doped semiconductor material is elevationally between and electrically couples the upper and lower stack channel pillars together. The conductively-doped semiconductor material comprises a first conductivity-producing dopant.
    Type: Application
    Filed: April 17, 2019
    Publication date: August 8, 2019
    Applicant: Micron Technology, Inc.
    Inventors: John D. Hopkins, David Daycock, Yushi Hu, Christopher Larsen, Dimitrios Pavlopoulos
  • Patent number: 10304853
    Abstract: Some embodiments include a memory array which has a vertical stack of alternating insulative levels and wordline levels. The wordline levels have terminal ends corresponding to control gate regions. Charge-trapping material is along the control gate regions of the wordline levels and not along the insulative levels. The charge-trapping material is spaced from the control gate regions by charge-blocking material. Channel material extends vertically along the stack and is laterally spaced from the charge-trapping material by dielectric material. Some embodiments include methods of forming NAND memory arrays.
    Type: Grant
    Filed: July 10, 2018
    Date of Patent: May 28, 2019
    Assignee: Micron Technology, Inc.
    Inventors: David Daycock, Richard J. Hill, Christopher Larsen, Woohee Kim, Justin B. Dorhout, Brett D. Lowe, John D. Hopkins, Qian Tao, Barbara L. Casey