Abstract: A chip-to-chip integration process for rapid prototyping of silicon avalanche photodiode (APD) arrays has been developed. This process has several advantages over wafer-level 3D integration, including: (1) reduced cost per development cycle since a dedicated full-wafer read-out integrated circuit (ROIC) fabrication is not needed, (2) compatibility with ROICs made in previous fabrication runs, and (3) accelerated schedule. The process provides several advantages over previous processes for chip-to-chip integration, including: (1) shorter processing time as the chips can be diced, bump-bonded, and then thinned at the chip-level faster than in a wafer-level back-illumination process, and (2) the CMOS substrate provides mechanical support for the APD device, allowing integration of fast microlenses directly on the APD back surface. This approach yields APDs with low dark count rates (DCRs) and higher radiation tolerance for harsh environments and can be extended to large arrays of APDs.

Abstract: A new process that enables void-free direct-bonded MBE-passivated large-format image sensors is disclosed. This process can be used to produce thin large-area image sensors for UV and soft x-ray imaging. Such devices may be valuable in future astronomy missions or in the radiology field. Importantly, by controlling the hydrogen concentration in the silicon oxide layers of the image sensor and the support wafer, voids in the bonding interface can be significantly reduced or eliminated. This process can be applied to any wafer that includes active circuitry and requires a second wafer, such as a support wafer.

Abstract: A chip-to-chip integration process for rapid prototyping of silicon avalanche photodiode (APD) arrays has been developed. This process has several advantages over wafer-level 3D integration, including: (1) reduced cost per development cycle since a dedicated full-wafer read-out integrated circuit (ROIC) fabrication is not needed, (2) compatibility with ROICs made in previous fabrication runs, and (3) accelerated schedule. The process provides several advantages over previous processes for chip-to-chip integration, including: (1) shorter processing time as the chips can be diced, bump-bonded, and then thinned at the chip-level faster than in a wafer-level back-illumination process, and (2) the CMOS substrate provides mechanical support for the APD device, allowing integration of fast microlenses directly on the APD back surface. This approach yields APDs with low dark count rates (DCRs) and higher radiation tolerance for harsh environments and can be extended to large arrays of APDs.

Abstract: A new process that enables void-free direct-bonded MBE-passivated large-format image sensors is disclosed. This process can be used to produce thin large-area image sensors for UV and soft x-ray imaging. Such devices may be valuable in future astronomy missions or in the radiology field. Importantly, by controlling the hydrogen concentration in the silicon oxide layers of the image sensor and the support wafer, voids in the bonding interface can be significantly reduced or eliminated. This process can be applied to any wafer that includes active circuitry and requires a second wafer, such as a support wafer.

Abstract: Dislocation pile-ups in compositionally graded semiconductor layers are reduced or eliminated, thereby leading to increased semiconductor device yield and manufacturability. This is accomplished by introducing a semiconductor layer having a plurality of threading dislocations distributed substantially uniformly across its surface as a starting layer and/or at least one intermediate layer during growth and relaxation of the compositionally graded layer. The semiconductor layer may include a seed layer disposed proximal to the surface of the semiconductor layer and having the threading dislocations uniformly distributed therein.

Abstract: Dislocation pile-ups in compositionally graded semiconductor layers are reduced or eliminated, thereby leading to increased semiconductor device yield and manufacturability. This is accomplished by introducing a semiconductor layer having a plurality of threading dislocations distributed substantially uniformly across its surface as a starting layer and/or at least one intermediate layer during growth and relaxation of the compositionally graded layer. The semiconductor layer may include a seed layer disposed proximal to the surface of the semiconductor layer and having the threading dislocations uniformly distributed therein.

Abstract: An MTPV thermophotovoltaic chip comprising a photovoltaic cell substrate, micron/sub-micron gap-spaced from a juxtaposed heat or infrared radiation-emitting substrate, with a radiation-transparent intermediate window substrate preferably compliantly adhered to the photovoltaic cell substrate and bounding the gap space therewith.

Abstract: Dislocation pile-ups in compositionally graded semiconductor layers are reduced or eliminated, thereby leading to increased semiconductor device yield and manufacturability. This is accomplished by introducing a semiconductor layer having a plurality of threading dislocations distributed substantially uniformly across its surface as a starting layer and/or at least one intermediate layer during growth and relaxation of the compositionally graded layer. The semiconductor layer may include a seed layer disposed proximal to the surface of the semiconductor layer and having the threading dislocations uniformly distributed therein.

Abstract: Dislocation pile-ups in compositionally graded semiconductor layers are reduced or eliminated, thereby leading to increased semiconductor device yield and manufacturability. This is accomplished by introducing a semiconductor layer having a plurality of threading dislocations distributed substantially uniformly across its surface as a starting layer and/or at least one intermediate layer during growth and relaxation of the compositionally graded layer. The semiconductor layer may include a seed layer disposed proximal to the surface of the semiconductor layer and having the threading dislocations uniformly distributed therein.

Abstract: An improved submicron gap thermophotovoltaic structure and method comprising an emitter substrate with a first surface for receiving heat energy and a second surface for emitting infrared radiation across an evacuated submicron gap to a juxtaposed first surface of an infrared radiation-transparent window substrate having a high refractive index. A second surface of the infrared radiation-transparent substrate opposite the first surface is affixed to a photovoltaic cell substrate by an infrared-transparent compliant adhesive layer. Relying on the high refractive index of the infrared radiation-transparent window substrate, the low refractive index of the submicron gap and Snell's law, the infrared radiation received by the first surface of the infrared radiation-transparent window substrate is focused onto a more perpendicular path to the surface of the photovoltaic cell substrate. This results in increased electrical power output and improved efficiency by the thermophotovoltaic structure.

Abstract: Dislocation pile-ups in compositionally graded semiconductor layers are reduced or eliminated, thereby leading to increased semiconductor device yield and manufacturability. This is accomplished by introducing a semiconductor layer having a plurality of threading dislocations distributed substantially uniformly across its surface as a starting layer and/or at least one intermediate layer during growth and relaxation of the compositionally graded layer. The semiconductor layer may include a seed layer disposed proximal to the surface of the semiconductor layer and having the threading dislocations uniformly distributed therein.

Abstract: An MTPV thermophotovoltaic chip comprising a photovoltaic cell substrate, micron/sub-micron gap-spaced from a juxtaposed heat or infrared radiation-emitting substrate, with a radiation-transparent intermediate window substrate preferably compliantly adhered to the photovoltaic cell substrate and bounding the gap space therewith.

Abstract: An MTPV thermophotovoltaic chip comprising a photovoltaic cell substrate, micron/sub-micron gap-spaced from a juxtaposed heat or infrared radiation-emitting substrate, with a radiation-transparent intermediate window substrate preferably compliantly adhered to the photovoltaic cell substrate and bounding the gap space therewith.

Abstract: A near-field energy conversion method, utilizing a sub-micrometer “near-field” gap between juxtaposed infrared radiation receiver and emitter surfaces, wherein compliant membrane structures, preferably fluid-filled, are interposed in the structure for maintaining uniform gap separation. Thermally resistant gap spacers are also used to maintain uniform gap separation. Means are provided for cooling a receiver substrate structure and for conducting heat to an emitter substrate structure. The gap may also be evacuated for more effective operation.

Abstract: A semiconductor structure may include a polycrystalline substrate comprising a metal, the polycrystalline substrate having substantially randomly oriented grains, as well as a buffer layer disposed thereover. The buffer layer may comprise a plurality of islands having an average island spacing therebetween. A polycrystalline semiconductor layer is disposed over the buffer layer.

Abstract: Dislocation pile-ups in compositionally graded semiconductor layers are reduced or eliminated, thereby leading to increased semiconductor device yield and manufacturability. This is accomplished by introducing a semiconductor layer having a plurality of threading dislocations distributed substantially uniformly across its surface as a starting layer and/or at least one intermediate layer during growth and relaxation of the compositionally graded layer. The semiconductor layer may include a seed layer disposed proximal to the surface of the semiconductor layer and having the threading dislocations uniformly distributed therein.

Abstract: A near-field energy conversion method, utilizing a sub-micrometer “near-field” gap between juxtaposed infrared radiation receiver and emitter surfaces, wherein compliant membrane structures, preferably fluid-filled, are interposed in the structure for maintaining uniform gap separation. Thermally resistant gap spacers are also used to maintain uniform gap separation. Means are provided for cooling a receiver substrate structure and for conducting heat to an emitter substrate structure. The gap may also be evacuated for more effective operation.

Abstract: Dislocation pile-ups in compositionally graded semiconductor layers are reduced or eliminated, thereby leading to increased semiconductor device yield and manufacturability. This is accomplished by introducing a semiconductor layer having a plurality of threading dislocations distributed substantially uniformly across its surface as a starting layer and/or at least one intermediate layer during growth and relaxation of the compositionally graded layer. The semiconductor layer may include a seed layer disposed proximal to the surface of the semiconductor layer and having the threading dislocations uniformly distributed therein.

Abstract: A near-field energy conversion structure and method of assembling the same, utilizing a sub-micrometer “near field” gap between juxtaposed photocell infrared radiation receiver and heat emitter surfaces, wherein compliant membrane structures, preferably fluid-filled, are interposed in the structure.

Abstract: Dislocation pile-ups in compositionally graded semiconductor layers are reduced or eliminated, thereby leading to increased semiconductor device yield and manufacturability. This is accomplished by introducing a semiconductor layer having a plurality of threading dislocations distributed substantially uniformly across its surface as a starting layer and/or at least one intermediate layer during growth and relaxation of the compositionally graded layer. The semiconductor layer may include a seed layer disposed proximal to the surface of the semiconductor layer and having the threading dislocations uniformly distributed therein.