Abstract: State of the art Integrated Circuits (ICs) encompass a variety of circuits, which have a wide variety of contact densities as measured in regions from 10 to 1000 microns in size. Fabrication processes for contacts have difficulty with high and low contact densities on the same IC, leading to a high incidence of electrical shorts and reduced operating speed of the circuits. This problem is expected to worsen as feature sizes shrink in future technology nodes. This invention is an electrically non-functional contact, known as a dummy contact, that is utilized to attain a more uniform distribution of contacts across an IC, which allows contact fabrication processes to produce ICs with fewer defects, and a method for forming said dummy contacts in ICs.

Abstract: An embodiment relates generally to a chemical mechanical polishing apparatus. The apparatus includes a platen adapted to receive a wafer to be chemical-mechanically polished and a polishing pad configured to polish the wafer. The apparatus also includes a slurry feed line configured to provide slurry to the polishing pad and at least one slurry dispensing outlet coupled to the slurry feed line and configured to dispense slurry as a mist of small droplets ranging from submicron to about 500 microns.

Abstract: Methods (102) are presented for protecting copper structures (26) from corrosion in the fabrication of semiconductor devices (2), wherein a thin semiconductor or copper-semiconductor alloy corrosion protection layer (30) is formed on an exposed surface (26a) of a copper structure (26) prior to performance of metrology operations (206), so as to inhibit corrosion of the copper structure (26). All or a portion of the corrosion protection layer (30) is then removed (214) in forming an opening in an overlying dielectric (44) in a subsequent interconnect layer.

Abstract: Semiconductor devices and manufacturing methods therefor are disclosed, in which conductive fill structures are provided in fill regions in an interconnect wiring layer between conductive wiring structures to facilitate planarization uniformity during metalization processing. One approach employs fill structures of varying sizes where smaller fill structures are formed near wiring regions having high aspect ratio wiring structures and larger fill structures are located near wiring regions with lower aspect ratio wiring structures. Another approach provides fill structures with varying amounts of openings, with fill structures having few or no openings being provided near low aspect ratio wiring structures and fill structures having more openings being located near higher aspect ratio wiring structures.