Abstract: In the course of unit timing, there exists the possibility for a non-compute (N/C) on a particular net in an IC chip design, which could be caused by numerous things, including but not limited to a pin being tied to power, a floating output, or invalid timing test for a given phase at a test point. A process automatically verifies that all non-computes are understood and exist for valid reasons, in order to ensure all necessary paths are being timed. The process takes a conventional Comprehensive Report output of a unit timing run and generates macro specific N/C reports for designers to review and sign off on.

Abstract: Disclosed is a method and apparatus for arbitration between multiple pipelines over shared resources for an SMP computer system. The computer includes logic to defer arbitration until later in the pipeline to help reduce latency to each pipeline. Also, introduced is the concept of retry tags for better priority to avoid lock-out. The system also includes round-robin tokens to manage rejected requests to allow better fairness on conflicts. While the processing logic employed specifically applies to cross-interrogation, the logic can be extended to other common resources. The illustrated SMP computer system also has self-correcting logic to maintain good round-robin tokens.

Abstract: Best and most recent NDR types are selected for all RLM's in a design in order to achieve timing closure. The selection employed uses two levels of filtering to examine the NDR types for each RLM, and based on the outcome of the filtering selects the most appropriate NDR type for input to the timing analysis. In one arrangement, the selection scheme is completely automated and is performed at the beginning of a timing analysis via script-driven processes.

Abstract: Best and most recent NDR types are selected for all RLM's in a design in order to achieve timing closure. The selection employed uses two levels of filtering to examine the NDR types for each RLM, and based on the outcome of the filtering selects the most appropriate NDR type for input to the timing analysis. In one arrangement, the selection scheme is completely automated and is performed at the beginning of a timing analysis via script-driven processes.

Abstract: In the course of unit timing, there exists the possibility for a non-compute (N/C) on a particular net in an IC chip design, which could be caused by numerous things, including but not limited to a pin being tied to power, a floating output, or invalid timing test for a given phase at a test point. A process automatically verifies that all non-computes are understood and exist for valid reasons, in order to ensure all necessary paths are being timed. The process takes a conventional Comprehensive Report output of a unit timing run and generates macro specific N/C reports for designers to review and sign off on.

Abstract: The invention relates to layout of circuit components, including determining the interconnections, buffers, or path nets between circuit blocks or circuit components and input/output bonding pads. This is accomplished by a method and program product that optimizes timing comprising. Wiring layout and buffer insertion is accomplished by setting all wires in the design to an initial best possible value, inserting buffers in longest nets of wires of the design, and degrading the resulting nets. This is accomplished by a wire sizing routine which takes the nets and degrades them accordingly. This degrading is done through a combination of one or more of knocking the wires down to lower levels and reducing their thickness. The amount of degradation is dependent on the final slack.

Abstract: In a hierarchical semiconductor digital unit comprised of a plurality of macro functional logic blocks, each of said macro functional logic blocks comprised of a plurality of leaf cells, each of said leaf cells accessed via an input terminal and an output terminal, the improvement wherein locating each input terminal provides access to a single leaf cell at a legal location proximate the leaf cell to which the input terminal provides access.

Abstract: In a hierarchical semiconductor digital unit comprised of a plurality of macro functional logic blocks, each of said macro functional logic blocks comprised of a plurality of leaf cells, each of said leaf cells accessed via an input terminal and an output terminal, the improvement wherein locating each input terminal provides access to a single leaf cell at a legal location proximate the leaf cell to which the input terminal provides access

Abstract: Disclosed is a method and apparatus for arbitration between multiple pipelines over shared resources for an SMP computer system. The computer includes logic to defer arbitration until later in the pipeline to help reduce latency to each pipeline. Also, introduced is the concept of retry tags for better priority to avoid lock-out. The system also includes round-robin tokens to manage rejected requests to allow better fairness on conflicts. While the processing logic employed specifically applies to cross-interrogation, the logic can be extended to other common resources. The illustrated SMP computer system also has self-correcting logic to maintain good round-robin tokens.