Patents by Inventor Christopher M. Dougherty

Christopher M. Dougherty has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Class D amplifier circuitry
    Patent number: 11799426
    Abstract: Class D amplifier circuitry comprising: input buffer circuitry configured to receive a first digital input signal modulated according to a first modulation scheme in which the digital input signal can take a first plurality N of discrete signal levels; analog modulator circuitry configured to generate an analog modulated signal based on an analog output signal output by the input buffer circuitry; and quantizer circuitry configured to generate an output signal based on the analog modulated signal, wherein the output signal is modulated according to a second modulation scheme in which the output signal can take a second plurality M of discrete signal levels, wherein the second plurality M is greater than the first plurality N.
    Type: Grant
    Filed: November 30, 2021
    Date of Patent: October 24, 2023
    Assignee: Cirrus Logic Inc.
    Inventors: Johnny Klarenbeek, David P. Singleton, Morgan T. Prior, Jonathan T. Wigner, Christopher M. Dougherty, Qi Cai, Anindya Bhattacharya
  • CLASS D AMPLIFIER CIRCUITRY
    Publication number: 20230170850
    Abstract: Class D amplifier circuitry comprising: input buffer circuitry configured to receive a first digital input signal modulated according to a first modulation scheme in which the digital input signal can take a first plurality N of discrete signal levels; analog modulator circuitry configured to generate an analog modulated signal based on an analog output signal output by the input buffer circuitry; and quantizer circuitry configured to generate an output signal based on the analog modulated signal, wherein the output signal is modulated according to a second modulation scheme in which the output signal can take a second plurality M of discrete signal levels, wherein the second plurality M is greater than the first plurality N.
    Type: Application
    Filed: November 30, 2021
    Publication date: June 1, 2023
    Applicant: Cirrus Logic International Semiconductor Ltd.
    Inventors: Johnny KLARENBEEK, David P. SINGLETON, Morgan T. PRIOR, Jonathan T. WIGNER, Christopher M. DOUGHERTY, Qi CAI, Anindya BHATTACHARYA
  • GLITCH MITIGATION IN SELECTABLE OUTPUT CURRENT MIRRORS WITH DEGENERATION RESISTORS
    Publication number: 20210286393
    Abstract: A selectable output current mirror may include a reference leg configured to generate a reference current, an output leg electrically coupled to the reference leg in a manner such that the output leg is configured to generate at an output of the output leg an output current proportional to the reference current, wherein the output leg comprises an output leg transistor, a drain path switch coupled between a first non-gate terminal of the output leg transistor and the output of the output leg, and a series combination of a degeneration resistor and a degeneration path switch coupled between a second non-gate terminal of the output leg transistor and a voltage source to the selectable output current mirror.
    Type: Application
    Filed: March 11, 2020
    Publication date: September 16, 2021
    Applicant: Cirrus Logic International Semiconductor Ltd.
    Inventors: Christopher M. DOUGHERTY, Anindya BHATTACHARYA, Vaibhav PANDEY, Ying OU
  • Glitch mitigation in selectable output current mirrors with degeneration resistors
    Patent number: 11119524
    Abstract: A selectable output current mirror may include a reference leg configured to generate a reference current, an output leg electrically coupled to the reference leg in a manner such that the output leg is configured to generate at an output of the output leg an output current proportional to the reference current, wherein the output leg comprises an output leg transistor, a drain path switch coupled between a first non-gate terminal of the output leg transistor and the output of the output leg, and a series combination of a degeneration resistor and a degeneration path switch coupled between a second non-gate terminal of the output leg transistor and a voltage source to the selectable output current mirror.
    Type: Grant
    Filed: March 11, 2020
    Date of Patent: September 14, 2021
    Assignee: Cirrus Logic, Inc.
    Inventors: Christopher M. Dougherty, Anindya Bhattacharya, Vaibhav Pandey, Ying Ou