Patents by Inventor Christopher M. Foster

Christopher M. Foster has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20150155162
    Abstract: An approach is developed to use an acidic rinse to reduce charge during the lithographic process, and thereby eliminate the crystalline damage and associated yield loss associated with the accumulated charge. The crystalline damage has been found to occur for certain thicknesses of dielectric layers, and such damage is irreparable. A sparge can be used to dissolve carbon dioxide in water to provide a weak acidic rinse.
    Type: Application
    Filed: December 3, 2013
    Publication date: June 4, 2015
    Applicant: Spansion LLC
    Inventors: Daniel E. SUTTON, Christopher M. FOSTER, Kelley Kyle HIGGINS, SR., Moutasim KHOGLY, Alexander J. BIERWAG, Daniel H. WILCOX
  • Patent number: 7307002
    Abstract: A method is disclosed for the definition of the poly-1 layer in a semiconductor wafer. A non-critical mask is used to recess field oxides in the periphery prior to poly-1 deposition by an amount equal to the final poly-1 thickness. A complimentary non-critical mask is used to permit CMP of the core to expose the tops of core oxide mesas from the shallow isolation trenches.
    Type: Grant
    Filed: April 4, 2005
    Date of Patent: December 11, 2007
    Assignee: Spansion LLC
    Inventors: Unsoon Kim, Hiroyuki Kinoshita, Yu Sun, Krishnashree Achuthan, Christopher H. Raeder, Christopher M. Foster, Harpreet Kaur Sachar, Kashmir Singh Sahota
  • Patent number: 6995437
    Abstract: A method for forming a semiconductor device that includes a line and space pattern with variable pitch and critical dimensions in a layer on a substrate. The substrate includes a first region (e.g., a core region) and a second region (e.g., a periphery region). A first sub-line and space pattern in the first region comprises a space of a dimension (A) less than achievable by lithographic processes alone. Further, a second sub-line and space pattern in the second region comprises at least one line including a second critical dimension (B) achievable by lithography. The method uses two critical masking steps to form a hard mask that includes in the core region a critical dimension (A) less than achievable at a resolution limit of lithography. Further, the method uses a single etch step to transfer the pattern of the hard mask to the layer.
    Type: Grant
    Filed: June 16, 2004
    Date of Patent: February 7, 2006
    Assignee: Advanced Micro Devices, Inc.
    Inventors: Hiroyuki Kinoshita, Yu Sun, Basab Banerjee, Christopher M. Foster, John R. Behnke, Cyrus Tabery
  • Patent number: 6780708
    Abstract: A method for forming a semiconductor device that includes a line and space pattern with variable pitch and critical dimensions in a layer on a substrate. The substrate includes a first region (e.g., a core region) and a second region (e.g., a periphery region). A first sub-line and space pattern in the first region comprises a space of a dimension (A) less than achievable by lithographic processes alone. Further, a second sub-line and space pattern in the second region comprises at least one line including a second critical dimension (B) achievable by lithography. The method uses two critical masking steps to form a hard mask that includes in the core region a critical dimension (A) less than achievable at a resolution limit of lithography. Further, the method uses a single etch step to transfer the pattern of the hard mask to the layer.
    Type: Grant
    Filed: March 5, 2003
    Date of Patent: August 24, 2004
    Assignee: Advanced Micro Devices, Inc.
    Inventors: Hiroyuki Kinoshita, Yu Sun, Basab Banerjee, Christopher M. Foster, John R. Behnke, Cyrus Tabery