Abstract: A solar tracker operates on a single axis, but partially simulates a dual-axis tracker by adjusting tilt angle as the tracker rotates. The tracker is disclosed in particular embodiments which fit efficiently within a hemispherical transparent dome.

Abstract: A microprocessor which has a secure read only memory is disclosed. The secure read only memory provides for storage of a program and security to protect that program.

Abstract: An architecture for a serial multi-chip package digital controller including a controller oriented processor die and a separate non-volatile memory die. The architecture provides for a low pin count on the package, minimal electrical connections on and between the dice, and a minimal number of registers by making use of significant multiplexing to allow many of the registers and signal lines to serve multiple functions responsive to the mode of operation and other control signals.An input data register on the non-volatile memory die and a related multiplexer allows data from different sources to be loaded into the input data register depending on the mode of operation. Also, the output of the input data register is coupled to plural locations so that the destination of the data can also be switched responsive to the mode of operation.

Abstract: An architecture for a serial multi-chip package digital controller including a controller oriented processor die and a separate non-volatile memory die. The architecture provides for a low pin count on the package, minimal electrical connections on and between the dice, and a minimal number of registers by making use of significant multiplexing to allow many of the registers and signal lines to serve multiple functions responsive to the mode of operation and other control signals.

Abstract: An architecture for a serial multi-chip package digital controller including a controller oriented processor die and a separate non-volatile memory die. The architecture provides for a low pin count on the package, minimal electrical connections on and between the dice, and a minimal number of registers by making use of significant multiplexing to allow many of the registers and signal lines to serve multiple functions responsive to the mode of operation and other control signals. A plurality of feed-throughs are provided on the non-volatile memory die to provide communication paths from the processor die to package pads which are in the shadow of the non-volatile memory die relative to the processor die and thus prevent direct connection from the processor die to the package pad. In normal run mode, these pads are exclusively used as feed-through, providing a direct connection between a specific pad on the processor die and a specific pad on the package.

Abstract: An architecture for a serial multi-chip package digital controller including a controller oriented processor die and a separate non-volatile memory die. The architecture provides for a low pin count on the package, minimal electrical connections on and between the dice, and a minimal number of registers by making use of significant multiplexing to allow many of the registers and signal lines to serve multiple functions responsive to the mode of operation and other control signals. A reset intercept circuit is provided on the non-volatile memory die for intercepting the signal which is provided to the reset input of the non-volatile memory die from external of the multi chip package. The reset intercept circuit provides a modified version thereof to the processor die. Particularly, the reset intercept circuit performs the function of sending a modified version of the reset signal to the processor die responsive to the present mode of operation of the multi chip package at the time the reset signal is received.

Abstract: An architecture for a serial multi-chip package digital controller including a controller oriented processor die and a separate non-volatile memory die. The architecture provides for a low pin count on the package, minimal electrical connections on and between the dice, and a minimal number of registers by making use of significant multiplexing to allow many of the registers and signal lines to serve multiple functions responsive to the mode of operation and other control signals.The processor includes an in-system programming mode including first and second memory interface control registers on the processor die and the memory die, respectively, for receiving control bits from the processor core for controlling multiplexers on the dies. The various bit output lines of the first memory interface control register are coupled to the control inputs of the multiplexers.

Abstract: An architecture for a serial multi-chip package digital controller including a controller oriented processor die and a separate non-volatile memory die. The architecture provides for a low pin count on the package, minimal electrical connections on and between the dice, and a minimal number of registers by making use of significant multiplexing to allow many of the registers and signal lines to serve multiple functions responsive to the mode of operation and other control signals.The processor can be programmed internally or externally. In the in-system programming mode, the processor program counter is used to fetch running instructions out of an on-board ROM instruction memory on the processor die. The processor core outputs an address into which data is to be programmed on its output data bus. The processor core then receives from an external device the data which is to be programmed into the selected address and outputs it serially onto the data bus and therefrom to the memory die.

Abstract: An EPROM register is programmed in a manner substantially similar to the manner used to program a main EPROM array contained on the same integrated circuit. Data in the main EPROM array must be read out by applying appropriate address and output enable signals. The EPROM register allows the data stored therein to be available at all times by providing a full-time static output signal. The register includes a static evaluation circuit for determining the data stored in the register, a precharge keeper circuit for providing a pseudo-static evaluation of the data, as well as providing a periodic refresh of the sense node during pseudo-static evaluation, and a margin test circuit for testing the threshold voltage of the register, as well as actual or relative shifts in the threshold voltage. The EPROM register serves as a nonvolatile memory which can be written to store configuration information for an integrated circuit.

Abstract: An integrated circuit which will produce a switched output when the circuit power supply drops a predetermined level below which reliable IC operation is not assured. This reduced power supply condition is referred to as brownout wherein the switching is related to the active devices. A preferred CMOS circuit is disclosed. The switching level is related to the N channel and P channel transistor sum of thresholds which makes the CMOS circuit process adaptive. The circuit is provided with a transistor gate oxide capacitor for improving noise immunity while achieving maximum utilization of IC chip area. In addition, output enable and circuit shutdown capabilities are detailed.

Abstract: A fault tolerant circuit and method of synchronizing multiple asynchronous input signals, such as reset signals, in a modular redundant fault-tolerant computer system in which clock signals or respective slices have a bounded skew with respect to one another. The input signal and clock signal for each slice of the system are used to produce an initial synchronization signal in each slice of a first layer of the circuit. Each initial synchronization signal is used with an inverted version of each of the slice clock signals to produce, in each slice of a second layer of the circuit, a set of local synchronization signals for each slice. The local synchronization signals for each slice are passed to a majority-voter which produces a voted output signal for the slice. The voted output signal and the clock signal for each slice are then used to produce a finally synchronized output signal for that slice.

Abstract: A Gray Code counter is provided having synchronous, modular circuits for each of the three types of bit positions, i.e., least significant bit ("LSB"), most significant bit ("MSB") and middle bit ("MB"). One LSB and MSB circuit each are used with as many MB circuits in between as are necessary to provide a counter having the desired number of bits. The LSB, MSB and MB circuits' designs are truly modular in that duplicate MB circuits can be freely coupled together between an LSB circuit and an MSB circuit to provide the desired number of counter bits without modifying any input or output interfaces between the circuits. The counter can count either up or down in accordance with a normal Gray Code sequence.

Abstract: A novel voltage selection circuit in which only one of a plurality of voltage levels is selected for application to an output node at any given time. Switching transistors are connected between the output node and associated reference voltages. Switching transistors are controlled by a set of voltage selection signals, each having logical zero and logical one states which are of sufficient magnitude to cause said switching transistors to turn on or turn off, and which are insured to be nonoverlapping. Two of the voltages are ground and VCC, which are switched by associated transistors using voltage selection signals having standard levels, such as ground and VCC. Another voltage VPPP is greater than VCC, and is switched by a switching transistor utilizing a voltage selection signal greater than VCC, preferably equal to VPPP. The wells of the second and third switching transistors are connected in common to VPPP to prevent junction breakdown when VPPP is selected.

Abstract: A unique circuit that unambiguously provides an output status bit and an output delta bit in response to an input data signal. This circuit does not require the use of a one shot. The circuit includes a first latch which latches the last status value, and an exclusive OR gate for comparing the previous input data value with the present input data value and provides an output data signal indicating whether change in the input data has occurred. If the exclusive OR gate indicates that a change in input data has occurred since the previous read, the new value of the input data is provided as an output status signal. Conversely, if the exclusive OR gate indicates that a change in the input signal has not occurred, the previous value of the input signal stored by the circuit is provided as an output status signal. Additional latches, which close at the onset of a read cycle, prevent either the delta bit or the status bit from changing during the read cycle.

Abstract: A method and structure is provided for powering down a plurality of clocks in a predetermined sequence. In one embodiment, a clock is powered down when it reaches a predefined logical level following the receipt of a power down signal. In another embodiment, a clock is powered down in response to a power down signal when the clock reaches a predefined level, and all clocks derived from that clock reach predefined levels. This is accomplished by including an edge sense circuit for determining when a clock reaches a predefined level, circuitry for combining a plurality of logical signals which indicate when the clock has reached said predefined level, and when all clocks derived from that clock have been powered down. Means and structure are also provided for powering down internal read/write control signals in response to a power down signal, thereby minimizing power consumption which would occur if the read/write control signals were switching during the power down cycle.