Abstract: Unitary transceiving units employ a multiple carrier, time-division-multiple-access (TDMA), time-division-duplex (TDD protocol to conduct concurrent wireless voice and data communications wherein a first transceiving base station unit tethered to a network interface wirelessly communicates to a second, mobile transceiving unit. The mobile transceiving unit wirelessly transmits and receives packetized voice and data information that is separated and routed to respective voice or data networks. The unitary mobile transceiving unit thus functions as a concurrent voice phone and data communications terminal/computer.

Abstract: A system and method employs standard DECT hardware adapted for use in the Industrial-Scientific-Medical (ISM) Spectrum wherein a Frequency Hopping Spread Spectrum (FHSS), multiple carrier, time-division-multiple-access (TDMA), time-division-duplex (TDD) technique provides wireless communications over the ISM Spectrum while employing standard DECT hardware. A baseband processor provides slot and frame timing to a RF sub-module wherein the preferred, although not exclusive number of carrier frequencies is programmed to seventy-five ranging between 2401.122 MHz to 2479.813 MHz and spaced 1.063 MHz apart and wherein each of the seventy-five channels supports a ten-millisecond frame preferably, although not exclusively, comprised of sixteen time slots.

Abstract: There is disclosed an apparatus for providing a virtual PCI device for use in a processing system comprising a data processor having an external peripheral bus coupled thereto in which peripheral devices associated with the external peripheral bus are controlled by accessing configuration circuitry associated with each of the peripheral devices. The apparatus comprises: a) an address trap circuit for detecting a configuration cycle accessing a virtual configuration address space associated with the virtual PCI device and generating an enable signal in response and b) an interrupt generation circuit associated with the address trap circuit that receives the enable signal and, in response, generates an interrupt signal that causes the data processor to execute instructions stored in system memory associated with the virtual device.

Abstract: In a computer system, a multi-port bus controller interposed between a CPU, system memory, and an expansion bus detects when a CPU access is to non-cacheable address space and begins a bus cycle to access the data before receiving a "miss" from a cache coupled to the CPU. By detecting non-cacheable address space independently and in parallel with the cache miss determination, the multi-port bus controller saves from one to three clock cycles in each bus cycle that accesses non-cacheable address space.

Abstract: A spin buffer and associated method assure data integrity in shared resources in a computer system. Concurrent accesses to different semaphores by different devices are allowed. Lock and identification data within the semaphore is cached in the spin buffer so a device requesting access to a shared resource that corresponds to a semaphore that is represented in the spin buffer may determine whether any other device has ownership of the shared resource by accessing the data within the spin buffer, rather than reading from the semaphore. By caching semaphore lock information and allowing concurrent accesses to different semaphores by different devices, enhances system performance is achieved.

Abstract: A highly integrated central processing unit employs a single external physical bus having first and second protocols to support an L2 cache and a general purpose peripheral interface respectively, to avoid bond-out of the CPU bus to the external world and to steal unused bandwidth for L2 cache accesses while maintaining a standard peripheral bus interface.

Abstract: A cache bus snoop protocol optimizes performance of a multiprocessor computer system with multiple level two caches by allocating windows of cache bus snoop activity on a need basis. When a cycle to cacheable address space is requested, the cache bus is granted only after the necessary snoop and write-back cycles are completed. During the snoop and write-back cycles, snoop activity by other devices in inhibited.

Abstract: Methods and system for memory control in a computer system having a store-in cache. In response to main memory read or write requests from a secondary processor, data is transferred into a buffer during a snoop cycle to the store-in cache. The data in the buffer is merged with write-back data from the store-in cache in a write operation. Data is provided directly from the buffer to the secondary processor and to main memory in a read operation. The buffer can be placed on a memory controller of the computer system. A second store-in cache can also be used for main memory transfers.

Abstract: Methods and system for memory control in a computer system having a store-in cache. In response to main memory read or write requests from a secondary processor, data is transferred into a buffer during a snoop cycle to the store-in cache. The data in the buffer is merged with write-back data from the store-in cache in a write operation. Data is provided directly from the buffer to the secondary processor and to main memory in a read operation. The buffer can be placed on a memory controller of the computer system. A second store-in cache can also be used for main memory transfers.

Abstract: The present invention relates to a computer system and method of using the same in which add-on memory cards are provided which have error correction code logic on the card and logic to do partial writes of data words. The system has a central processing unit (CPU), and a BUS interconnecting the CPU and the add-on memory cards which are configured to write data and read data from the add-on memory. The system is further configured (either within the CPU or as a separate function) to generate parity bits associated with each of the bytes of data the CPU writes to the add-on memory and to read parity bits associated with data the CPU reads from the add-on memory and regenerate new parity bits and compare the newly generated parity bits with the original parity bits to detect data errors on data read from the add-on memory.

Abstract: A write compression buffer is connected to a CPU bus and to a memory controller to provide write cycle compression in which plural partial write requests to the same memory address are compressed into a single memory write cycle. The buffer has a plurality of buffering level.

Abstract: The present invention provides a computer system and method of using the same. Add-on memory cards for the system are provided which cards have error correction code logic on the card, and logic to do partial writes of data words. The system has a central processing unit (CPU), a BUS interconnecting the CPU and the add-on memory cards. The CPU or associated components are configured to write data and read data from the add-on memory as several data bytes constituting data words. The system is further configured either within the CPU or as a separate function to generate parity bits associated with each of the bytes of data the CPU writes to the add-on memory and to read parity bits associated with data the CPU reads from the add-on memory and regenerate new parity bits and compare the newly generated parity bits with the original parity bits to detect data errors on data read from the add-on memory. The system itself does not contain error correction code (ECC).

Abstract: A method and system for managing the utilization of power is provided. In a system having one or more devices, such as a memory subsystem having one or more banks of memory, the amount of power necessary for the operation of one or more of the devices is monitored and if possible, the power being supplied to one or more of the devices is reduced. A scoreboard located within a memory controller is used to retain the available power modes for each of the devices. When it is determined that it is desirable to reduce the power being supplied to a particular device, then the scoreboard is accessed in order to determine the lowest power level available for the device. Using this information, an amount of power commensurate with the lowest power level is applied to the device, thereby reducing the amount of power being applied to the device. In one aspect of the invention, a device is automatically placed in its lowest power level when it has not been accessed for a preselected amount of time.

Abstract: A computer system is provided which includes a CPU having a memory controller interconnecting the CPU to a bus. The bus has card receptacles having pin receiving sockets electrically connected to the bus to receive the pins of memory cards. The memory controller is connected to logic which will identify the type of memory card which is inserted in the pin sockets. From this identification combinational logic is provided that, in response to the identification of the type of card, will direct the appropriate signals from the memory controller to the appropriate sockets depending upon which type of card is plugged into the socket. In this way, a given socket configuration can accept different types of memory cards having different pin signal configurations without physical modification of the sockets.