Abstract: A phase detector includes data detection logic for detecting data in a communication signal, amplitude detection logic for processing modulation chosen from any of a PAM2 and a PAM4 communication modality, in-phase edge detection logic for detecting in-phase edge information in the communication signal, quadrature edge detection logic for detecting quadrature edge information in the communication signal, and mixing logic for determining an amount of in-phase edge information and quadrature edge information to be applied based on at least one channel parameter in the communication channel.

Abstract: A phase detector includes data detection logic for detecting data in a communication signal, amplitude detection logic for processing modulation chosen from any of a PAM2 and a PAM4 communication modality, in-phase edge detection logic for detecting in-phase edge information in the communication signal, quadrature edge detection logic for detecting quadrature edge information in the communication signal, and mixing logic for determining an amount of in-phase edge information and quadrature edge information to be applied based on at least one channel parameter in the communication channel.

Abstract: A system and method for evaluating a device under test (DUT) that utilizes a model of the DUT interfaced to DUT interface logic, which is designed to interface the DUT to automated testing equipment (ATE). By ensuring that the model includes a description of the DUT and of the DUT testing interface, conditions such as connections between ports of the IC (i.e., buddying) that may or may not be interfaced to the ATE may be included in the model to enable precise test pattern sets to be generated using the model. The test pattern sets may be used by a simulator to test the design of an IC or by ATE to test a fabricated IC having the design.

Abstract: A system and method for evaluating a device under test (DUT) that utilizes a model of the DUT interfaced to DUT interface logic, which is designed to interface the DUT to automated testing equipment (ATE). By ensuring that the model includes a description of the DUT and of the DUT testing interface, conditions such as connections between ports of the IC (i.e., buddying) that may or may not be interfaced to the ATE may be included in the model to enable precise test pattern sets to be generated using the model. The test pattern sets may be used by a simulator to test the design of an IC or by ATE to test a fabricated IC having the design.

Abstract: An integrated circuit incorporating test access provisions and a system addressable command control register; and provisions for selectably enabling and accessing one or the other for purposes of evaluating integrated circuit functionality.