Abstract: An adaptive patterning method and system for fabricating panel based package structures is described. Misalignment for individual device units in a panel or reticulated wafer may be adjusted for by measuring the position of each individual device unit and forming a unit-specific pattern over each of the respective device units.

Abstract: A method of panelized packaging is described in which a plurality of die units are placed on a dielectric film. The dielectric film is then cured to lock the plurality of die units in place, which are then encapsulated. The cured dielectric film is then patterned utilizing a mask-less patterning technique.

Abstract: A thermal via heat spreader package includes an electronic component having an active surface including a nonfunctional region. A package body encloses the electronic component, the package body comprising a principal surface. Thermal vias extend from the principal surface through at least a portion of the package body and towards the nonfunctional region. A heat spreader is thermally connected to the thermal vias. Heat generated by the electronic component is dissipated to the thermal vias and to the heat spreader. The density of the thermal vias is increased in a hotspot of the electronic component thus maximizing heat transfer from the hotspot. In this manner, optimal heat transfer from the electronic component is achieved.

Abstract: A semiconductor device has a substrate having a plurality of metal layers. A die is coupled to the substrate. A plurality of metal wires is provided. At least one end of each of the metal wires is electrically coupled to at least one metal layer. A mold compound is used to encapsulate the die, a first surface of the substrate, and the plurality of metal wires. A portion of at least one metal wire remains exposed. A conductive coating is applied to the mold compound and to the portion of the at least one metal wire exposed.

Abstract: A sensor package has a substrate. A sensor die having an inactive surface is bonded to the substrate. An active surface of the sensor die is exposed. A portion of the active surface of the sensor die has an active imaging area. A metal bezel is formed on the active surface of the sensor die and separate from the imaging area.

Abstract: A semiconductor package has a first substrate having a plurality of metal traces. At least one die is electrically coupled to the first surface of the first substrate. A plurality of land pads is formed on the first surface of the first substrate. A mold compound encapsulates portions of the die and portions of the first surface of the first substrate. A conductive coating is applied to the mold compound and electrically coupled to at least one metal trace. A non-conductive coating is formed over the conductive coating and portions of the mold compound. A plurality of vias is formed through the non-conductive coating and the mold compound to expose the land pads.

Abstract: An interconnect structure (i.e., a laminate interposer) which is mounted to a semiconductor package leadframe or substrate prior to molding the package body of the semiconductor package. During the molding process, the top of the laminate interposer is protected such that the top surface of the interposer is exposed subsequent to the completion of the molding process. In this manner, electrical signals can be routed from the package leadframe or substrate to the top surface of the package body of the semiconductor package. Subsequently, a mating package can be mounted on top of the underlying package by way of a ball grid array (BGA) interconnect or other type of interconnect.

Abstract: A stacked redistribution layer (RDL) die assembly package includes a substrate, a first level RDL die assembly mounted to the substrate and a second level RDL die assembly mounted to the first level RDL die assembly. The first level RDL die assembly includes a first die comprising bond pads, a first fan out support extending outwardly from sides of the first die, and first traces electrically connected to the bond pads, the first traces being supported by the first fan out support. Similarly, the second level RDL die assembly includes a second die comprising bond pads, a second fan out support extending outwardly from sides of the second die, and second traces electrically connected to the bond pads of the second die, the second traces being supported by the second fan out support.

Abstract: A circuit element package has a substrate having a plurality of electrically conductive patterns, a die pad, and an access hole formed through the die pad and substrate. A plurality of leads is coupled to the substrate. A circuit element die is attached to the die pad wherein a first sensor port is positioned over the access hole. A die attach membrane is provided for attaching the circuit element die to the die pad. The die attach membrane allows the circuit element die to sense ambient while protecting the circuit element die from environmental damage. An encapsulant is used for covering portions of the circuit element die.

Abstract: The present invention comprises a semiconductor package comprising a bottom semiconductor package substrate which is populated with one or more electronic components. The electronic component(s) of the bottom substrate are covered or encapsulated with a suitable mold compound which hardens into a package body of the semiconductor package. The package body is provided with one or more vias through the completion of laser drilling process, such via(s) providing access to one or more corresponding conductive contacts of the bottom substrate. These vias are either lined or partially filled with a conductive metal material. Subsequently, a top semiconductor package substrate (which may optionally be populated with one or more electronic components) is mounted to the package body and electrically connected to the conductive metal within the via(s) of the package body.

Abstract: A semiconductor device has a substrate comprising at least one dielectric layer and at least one metal layer on a first surface of the substrate. A die is attached to the first surface of the substrate. A mold compound is used to encapsulate the die and partially encapsulate the first surface of the substrate. The mold compound has a protrusion proximate to the at least one metal layer. A conductive material covers the mold compound, including the protrusion, and contacts the at least one metal layer.

Abstract: In accordance with the present invention, there is provided various methods of simultaneously fabricating a plurality of semiconductor packages (e.g., cavity type semiconductor packages) wherein the singulation process is achieved using etching techniques as opposed to more conventional cutting techniques such as sawing or punching. Such etching techniques are inherently lower in cost and free from many of the defects induced by other cutting techniques.

Abstract: A stacked redistribution layer (RDL) die assembly package includes a substrate, a first level RDL die assembly mounted to the substrate and a second level RDL die assembly mounted to the first level RDL die assembly. The first level RDL die assembly includes a first die comprising bond pads, a first fan out support extending outwardly from sides of the first die, and first traces electrically connected to the bond pads, the first traces being supported by the first fan out support. Similarly, the second level RDL die assembly includes a second die comprising bond pads, a second fan out support extending outwardly from sides of the second die, and second traces electrically connected to the bond pads of the second die, the second traces being supported by the second fan out support.

Abstract: In accordance with the present invention, there is provided various methods of simultaneously fabricating a plurality of semiconductor packages (e.g., cavity type semiconductor packages) wherein the singulation process is achieved using etching techniques as opposed to more conventional cutting techniques such as sawing or punching. Such etching techniques are inherently lower in cost and free from many of the defects induced by other cutting techniques.

Abstract: A semiconductor device and method of manufacturing has a substrate having a plurality of metal layers. At least one metal layer is exposed on at least one side surface of the semiconductor device. A die is coupled to the substrate. A mold compound encapsulates the die and a top surface of the substrate. A conductive coating is applied to the mold compound and to at least one metal layer exposed on at least one side surface of the substrate.

Abstract: An electronic component (10) has an electrically insulating substrate (20) that is encapsulated with an electrically conductive material (15) to provide thermal dissipation for the electronic component (10). The electrically insulating substrate (20) has cavities (21-24) that are either completely filled with an electrically conductive material (15) or are partially filled to provide recesses (26-27) for electronic devices (30,31). The electronic devices (30,31) are electrically coupled to the leads (60-63) of the electronic component (10) using either wire bonds (70) or metallic depositions (55-57).

Abstract: An assembly substrate includes a substrate (11, 31, 41), a composite layer (12, 32, 42) overlying the substrate (11, 31, 41), and an electrically conductive layer (13, 33, 43) overlying the composite layer (12, 32, 42). The composite layer (12, 32, 42) includes a first material having an as-deposited tetragonal crystal structure and a second material. The second material in the composite layer (12, 32, 42) reduces the susceptibility of the composite layer (12, 32, 42) to fracture under stress.

Abstract: A hybrid multi-chip module includes semiconductor chips (27, 31) bonded to a base plate (24). The base plate includes a substrate (11) having two surfaces (12, 13) and a conductive material (16) molded on the two surfaces (12, 13). A coefficient of thermal expansion (CTE) mismatch between the substrate (11) and the conductive material (16) at the first surface (12) is balanced by a similar, but opposite, CTE mismatch between the substrate (11) and the conductive material (16) at the second surface (13). The CTE mismatch balance across the base plate (24) produces a base plate (24) having a substantially planar form at high temperatures.