Patents by Inventor Christopher M. Smitchger
Christopher M. Smitchger has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11923030Abstract: A system includes a memory device and a processing device, operatively coupled with the memory device, to perform operations including initiating a read operation with respect to a block of the memory device, selecting, based on a set of criteria, a default read offset from a set of read offsets, wherein the set of criteria includes at least one of: a parameter related to trigger rate, or an amount of time that an open block is allowed to remain open to control threshold voltage shift due to storage charge loss, and applying the default read offset to a read operation performed with respect to the block.Type: GrantFiled: August 16, 2022Date of Patent: March 5, 2024Assignee: Micron Technology, Inc.Inventors: Gary F. Besinga, Renato C. Padilla, Tawalin Opastrakoon, Sampath K. Ratnam, Michael G. Miller, Christopher M. Smitchger, Vamsi Pavan Rayaprolu, Ashutosh Malshe
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Publication number: 20240062835Abstract: A processing device in a memory sub-system detects an occurrence of a data integrity check trigger event and, responsive to the occurrence of the data integrity check trigger event, identifies a memory die of a plurality of memory dies. The processing device further associates each segment of the identified memory die with a respective group of a plurality of groups, each group representing one or more of a plurality of error mechanisms, and determines one or more respective adaptive scan frequencies for the identified memory die based on statistics of the segments associated with each respective group.Type: ApplicationFiled: August 19, 2022Publication date: February 22, 2024Inventors: Vamsi Pavan Rayaprolu, Christopher M. Smitchger, James Fitzpatrick, Patrick R. Khayat, Sampath K. Ratnam
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Patent number: 11810631Abstract: Systems and methods are disclosed including a memory device and a processing device operatively coupled to the memory device. The processing device can perform operations including determining a value of a data state metric of a memory page; responsive to the data state metric satisfying a first threshold criterion, determining a value of a voltage distribution metric associated with the page; and responsive to the voltage distribution metric value satisfying a second threshold criterion, performing a media management operation with respect to a block associated with the page.Type: GrantFiled: December 16, 2020Date of Patent: November 7, 2023Assignee: Micron Technology, Inc.Inventors: Vamsi Pavan Rayaprolu, Michael Sheperek, Christopher M. Smitchger
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Patent number: 11756636Abstract: Systems and methods are disclosed including a memory device and a processing device operatively coupled to the memory device. The processing device can perform operations including determining a value of a data state metric associated with data stored in a part of a block of the memory device; responsive to determining that the value of the data state metric satisfies a first threshold criterion, determining a first value reflecting a voltage distribution metric associated with at least the part of the block; determining a second value reflecting at least one of a deterioration slope indicative of a data deterioration rate associated with a first portion of the memory device or an error rate associated with a second portion of the memory device; feeding the first value and the second value to a neural network; and receiving, from the neural network, an instruction to perform a media management operation.Type: GrantFiled: September 7, 2022Date of Patent: September 12, 2023Assignee: Micron Technology, Inc.Inventors: Vamsi Pavan Rayaprolu, Christopher M. Smitchger
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Publication number: 20230268009Abstract: A system includes a memory device including an block and a processing device, operatively coupled with the memory device, to perform operations including initiating a page scan with respect to a page of the block, determining whether to perform an erased page check, and in response to determining that the erased page check is not to be performed, performing a two-sided page scan with calibration feedback.Type: ApplicationFiled: February 18, 2022Publication date: August 24, 2023Inventors: Christopher M. Smitchger, Vamsi Pavan Rayaprolu, Patrick R. Khayat, Hyung Seok Kim, Steven Michael Kientz
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Patent number: 11715531Abstract: A system includes a memory device and a processing device, operatively coupled with the memory device, to perform operations including identifying an amount of storage charge loss (SCL) that has occurred on an open block of the memory device, the open block having one or more erased pages, determining that the amount of SCL satisfies a threshold criterion corresponding to an acceptable amount of SCL to occur on the open block, and responsive to determining that the amount of SCL satisfies the threshold criterion, keeping the open block open for programming the one or more erased pages.Type: GrantFiled: March 24, 2021Date of Patent: August 1, 2023Assignee: Micron Technology, Inc.Inventors: Christopher M. Smitchger, Gary F. Besinga, Renato C. Padilla, Tawalin Opastrakoon, Sampath K. Ratnam, Michael G. Miller, Vamsi Pavan Rayaprolu, Ashutosh Malshe
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Patent number: 11715541Abstract: A method includes associating each block of a plurality of blocks of a memory device with a corresponding frequency access group of a plurality of frequency access groups based on corresponding access frequencies, and performing scan operations on blocks of each of the plurality of frequency access groups using a scan frequency that is different from scan frequencies of other frequency access groups. A scan operation performed on a frequency access group with a higher access frequency uses a higher scan frequency than a scan operation performed on a frequency access group with a lower access frequency.Type: GrantFiled: July 18, 2022Date of Patent: August 1, 2023Assignee: Micron Technology, Inc.Inventors: Renato C. Padilla, Sampath K. Ratnam, Christopher M. Smitchger, Vamsi Pavan Rayaprolu, Gary F. Besinga, Michael G. Miller, Tawalin Opastrakoon
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Publication number: 20230229317Abstract: Systems, methods, and apparatus related to controlling media scan in memory devices. In one approach, a controller manages a media scanning process for a memory (e.g., NAND flash memory) as a function of temperature. The controller collects temperature data from one or more sensors of the memory. Using the collected temperature data, the controller determines a moving average temperature. Based on the moving average temperature, the controller updates a frequency of the media scanning process.Type: ApplicationFiled: January 20, 2022Publication date: July 20, 2023Inventors: Saeed Sharifi Tehrani, Christopher M. Smitchger
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Patent number: 11687452Abstract: An amount of threshold voltage distribution shift is determined. The threshold voltage distribution shift corresponds to an amount of time after programming of a reference page of a block of a memory device. A program-verify voltage is adjusted based on the amount of threshold voltage distribution shift to obtain an adjusted program-verify voltage. Using the adjusted program-verify voltage, a temporally subsequent page of the block is programmed at a time corresponding to the amount of time after the programming of the reference page.Type: GrantFiled: December 16, 2020Date of Patent: June 27, 2023Assignee: Micron Technology, Inc.Inventors: Gary F. Besinga, Renato C. Padilla, Tawalin Opastrakoon, Sampath K. Ratnam, Michael G. Miller, Christopher M. Smitchger, Vamsi Pavan Rayaprolu, Ashutosh Malshe
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Publication number: 20230049877Abstract: A first host data item and a second host data item are received. The first host data item is stored in a first page of a first logical unit of a memory device, where the first page is one of a plurality of pages associated with redundancy metadata. A second page a second page of a second logical unit of the memory device is identified, where the second page is one of the plurality of pages associated with the redundancy metadata, and the first page and the second page are associated with different wordlines of the memory device. The second host data item is stored in the second page of the second logical unit of the memory device. The first page and the second page can be associated with a fault tolerant stripe that includes the redundancy metadata.Type: ApplicationFiled: October 31, 2022Publication date: February 16, 2023Inventors: Tawalin Opastrakoon, Renato C. Padilla, Michael G. Miller, Christopher M. Smitchger, Gary F. Besinga, Sampath K. Ratnam, Vamsi Pavan Rayaprolu
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Publication number: 20220415412Abstract: Systems and methods are disclosed including a memory device and a processing device operatively coupled to the memory device. The processing device can perform operations including determining a value of a data state metric associated with data stored in a part of a block of the memory device; responsive to determining that the value of the data state metric satisfies a first threshold criterion, determining a first value reflecting a voltage distribution metric associated with at least the part of the block; determining a second value reflecting at least one of a deterioration slope indicative of a data deterioration rate associated with a first portion of the memory device or an error rate associated with a second portion of the memory device; feeding the first value and the second value to a neural network; and receiving, from the neural network, an instruction to perform a media management operation.Type: ApplicationFiled: September 7, 2022Publication date: December 29, 2022Inventors: Vamsi Pavan Rayaprolu, Christopher M. Smitchger
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Publication number: 20220391102Abstract: A memory system includes a memory device and a processing device, operatively coupled to the memory device. The processing device performs operations comprising: identifying one or more mandatory scan wordlines of the memory device and one or more remaining wordlines of the memory device; performing a plurality of scan iterations with respect to a plurality of pages of the memory device, such that performing each scan iteration comprises: identifying, among the remaining wordlines, one or more scheduled scan wordlines of the memory device, scanning a subset of pages of the memory device that are addressable by the mandatory scan wordlines and the scheduled scan wordlines; wherein a combination of a first plurality of pages addressable by the scheduled scan wordlines selected by the plurality of scan iterations and a second plurality of pages addressable by the mandatory wordlines comprises the plurality of pages of the memory device.Type: ApplicationFiled: May 25, 2022Publication date: December 8, 2022Inventors: Vamsi Pavan Rayaprolu, Christopher M. Smitchger, Saeed Sharifi Tehrani
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Publication number: 20220392561Abstract: A system includes a memory device and a processing device, operatively coupled with the memory device, to perform operations including initiating a read operation with respect to a block of the memory device, selecting, based on a set of criteria, a default read offset from a set of read offsets, wherein the set of criteria includes at least one of: a parameter related to trigger rate, or an amount of time that an open block is allowed to remain open to control threshold voltage shift due to storage charge loss, and applying the default read offset to a read operation performed with respect to the block.Type: ApplicationFiled: August 16, 2022Publication date: December 8, 2022Inventors: Gary F. Besinga, Renato C. Padilla, Tawalin Opastrakoon, Sampath K. Ratnam, Michael G. Miller, Christopher M. Smitchger, Vamsi Pavan Rayaprolu, Ashutosh Malshe
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Publication number: 20220391127Abstract: A plurality of host data items, including a first host data item and a second host data item, are received. The second host data item consecutively follows the first host data item. The first host data item is stored in a first page of a first logical unit of the memory device, wherein the first page is associated with a first page number. A second page number is determined for the second host data item based on an offset value that corresponds to a number of pages per wordline of the memory device. A second logical unit of the memory device is identified. The second host data item is stored in a second page of the second logical unit, wherein the second page is identified by the second page number, and the first page and the second page are associated with a fault-tolerant stripe.Type: ApplicationFiled: June 4, 2021Publication date: December 8, 2022Inventors: Tawalin Opastrakoon, Renato C. Padilla, Michael G. Miller, Christopher M. Smitchger, Gary F. Besinga, Sampath K. Ratnam, Vamsi Pavan Rayaprolu
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Patent number: 11507304Abstract: A plurality of host data items, including a first host data item and a second host data item, are received. The second host data item consecutively follows the first host data item. The first host data item is stored in a first page of a first logical unit of the memory device, wherein the first page is associated with a first page number. A second page number is determined for the second host data item based on an offset value that corresponds to a number of pages per wordline of the memory device. A second logical unit of the memory device is identified. The second host data item is stored in a second page of the second logical unit, wherein the second page is identified by the second page number, and the first page and the second page are associated with a fault-tolerant stripe.Type: GrantFiled: June 4, 2021Date of Patent: November 22, 2022Assignee: MICRON TECHNOLOGY, INC.Inventors: Tawalin Opastrakoon, Renato C. Padilla, Michael G. Miller, Christopher M. Smitchger, Gary F. Besinga, Sampath K. Ratnam, Vamsi Pavan Rayaprolu
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Patent number: 11495309Abstract: Systems and methods are disclosed including a memory device and a processing device operatively coupled to the memory device. The processing device can perform operations including determining a voltage distribution metric associated with a at least part of a block of the memory device; determining a threshold value for the voltage distribution metric associated with the block; and responsive to determining that the voltage distribution metric exceeds the threshold value, performing a media management operation with respect to the block.Type: GrantFiled: December 16, 2020Date of Patent: November 8, 2022Assignee: MICRON TECHNOLOGY, INC.Inventors: Vamsi Pavan Rayaprolu, Christopher M. Smitchger
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Publication number: 20220351796Abstract: A method includes associating each block of a plurality of blocks of a memory device with a corresponding frequency access group of a plurality of frequency access groups based on corresponding access frequencies, and performing scan operations on blocks of each of the plurality of frequency access groups using a scan frequency that is different from scan frequencies of other frequency access groups. A scan operation performed on a frequency access group with a higher access frequency uses a higher scan frequency than a scan operation performed on a frequency access group with a lower access frequency.Type: ApplicationFiled: July 18, 2022Publication date: November 3, 2022Inventors: Renato C. Padilla, Sampath K. Ratnam, Christopher M. Smitchger, Vamsi Pavan Rayaprolu, Gary F. Besinga, Michael G. Miller, Tawalin Opastrakoon
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Publication number: 20220310190Abstract: A system includes a memory device and a processing device, operatively coupled with the memory device, to perform operations including receiving a set of read offsets for a block of the memory device, the set of read offsets comprising a default read offset, selecting the default read offset from the set of read offsets based on one or more criteria, applying the default read offset to a read operation performed with respect to the block, determining that a second set of criteria associated with removing the default read offset is satisfied, and removing the default read offset responsive to determining that the second set of criteria is satisfied.Type: ApplicationFiled: March 25, 2021Publication date: September 29, 2022Inventors: Gary F. Besinga, Renato C. Padilla, Tawalin Opastrakoon, Sampath K. Ratnam, Michael G. Miller, Christopher M. Smitchger, Vamsi Pavan Rayaprolu, Ashutosh Malshe
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Publication number: 20220310183Abstract: A system includes a memory device and a processing device, operatively coupled with the memory device, to perform operations including identifying an amount of storage charge loss (SCL) that has occurred on an open block of the memory device, the open block having one or more erased pages, determining that the amount of SCL satisfies a threshold criterion corresponding to an acceptable amount of SCL to occur on the open block, and responsive to determining that the amount of SCL satisfies the threshold criterion, keeping the open block open for programming the one or more erased pages.Type: ApplicationFiled: March 24, 2021Publication date: September 29, 2022Inventors: Christopher M. Smitchger, Gary F. Besinga, Renato C. Padilla, Tawalin Opastrakoon, Sampath K. Ratnam, Michael G. Miller, Vamsi Pavan Rayaprolu, Ashutosh Malshe
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Patent number: 11456051Abstract: A system includes a memory device and a processing device, operatively coupled with the memory device, to perform operations including receiving a set of read offsets for a block of the memory device, the set of read offsets comprising a default read offset, selecting the default read offset from the set of read offsets based on one or more criteria, applying the default read offset to a read operation performed with respect to the block, determining that a second set of criteria associated with removing the default read offset is satisfied, and removing the default read offset responsive to determining that the second set of criteria is satisfied.Type: GrantFiled: March 25, 2021Date of Patent: September 27, 2022Assignee: Micron Technology, Inc.Inventors: Gary F. Besinga, Renato C. Padilla, Tawalin Opastrakoon, Sampath K. Ratnam, Michael G. Miller, Christopher M. Smitchger, Vamsi Pavan Rayaprolu, Ashutosh Malshe