Patents by Inventor Christopher Malone
Christopher Malone has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11920361Abstract: A docking station for a medical device is described. In some examples, the docking station includes a frame and a base plate coupled to the frame. At least a portion of the base plate is coupled to a lower portion of the frame. In some examples, an electronic connector of the docking station is configured to couple to the medical device and to provide power to the medical device when the medical device is docked to the docking station. In some examples, a docking mechanism is coupled to an upper portion of the frame and configured to retain the medical device.Type: GrantFiled: March 26, 2021Date of Patent: March 5, 2024Assignee: PHYSIO-CONTROL, INC.Inventors: Barry D. Curtin, Alexander Hamilton, Kristina Edmonson, David Andrews, Christopher G. Alviar, Neal Stanley Clark, Benjamin Danziger, Christopher William Egbert, Jason Fouts, Matthew Malone, Joshua Berndt, Brigitta M. Suwandana, Jeremy Edward Brummett
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Patent number: 11895807Abstract: A data rack system includes a data center rack frame, a shelf positioned within the data center rack frame; and a modular battery unit disposed on the shelf. The modular battery unit further includes a housing having an outer surface, a plurality of strips of phase change material (“PCM”) attached to the outer surface and spaced apart from one another; and air flow channels. The air flow channels are formed in spaces between two adjacent strips of the plurality of strips and defined by a shape and size of the spaces between the two adjacent strips.Type: GrantFiled: May 28, 2020Date of Patent: February 6, 2024Assignee: Google LLCInventors: Madhusudan K. Iyengar, Melanie Beauchemin, Christopher Malone
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Patent number: 11348859Abstract: While the use of 2.5D/3D packaging technology results in a compact IC package, it also raises challenges with respect to thermal management. Integrated component packages according to the present disclosure provide a thermal management solution for 2.5D/3D IC packages that include a high-power component integrated with multiple lower-power components. The thermal solution provided by the present disclosure includes a mix of passive cooling by traditional heatsink or cold plate and active cooling by thermoelectric cooling (TEC) elements. Certain methods according to the present disclosure include controlling a temperature during normal operation in an IC package that includes a plurality of lower-power components located adjacent to a high-power component in which the high-power component generates a greater amount of heat relative to each of the lower-power components during normal operation.Type: GrantFiled: October 8, 2019Date of Patent: May 31, 2022Assignee: Google LLCInventors: Melanie Beauchemin, Madhusudan Iyengar, Christopher Malone, Gregory Imwalle
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Publication number: 20210378132Abstract: A data rack system includes a data center rack frame, a shelf positioned within the data center rack frame; and a modular battery unit disposed on the shelf. The modular battery unit further includes a housing having an outer surface, a plurality of strips of phase change material (“PCM”) attached to the outer surface and spaced apart from one another; and air flow channels. The air flow channels are formed in spaces between two adjacent strips of the plurality of strips and defined by a shape and size of the spaces between the two adjacent strips.Type: ApplicationFiled: May 28, 2020Publication date: December 2, 2021Inventors: Madhusudan K. Iyengar, Melanie Beauchemin, Christopher Malone
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Publication number: 20210378106Abstract: A method of manufacturing a chip assembly comprises joining an in-process unit to a printed circuit board; reflowing a bonding material disposed between and electrically connecting the in-process unit with the printed circuit board, the bonding material having a first reflow temperature; and then joining a heat distribution device to the plurality of semiconductor chips using a thermal interface material (“TIM”) having a second reflow temperature that is lower than the first reflow temperature. The in-process unit further comprises a substrate having an active surface, a passive surface, and contacts exposed at the active surface; an interposer electrically connected to the substrate; a plurality of semiconductor chips overlying the substrate and electrically connected to the substrate through the interposer, and a stiffener overlying the substrate and having an aperture extending therethrough, the plurality of semiconductor chips being positioned within the aperture.Type: ApplicationFiled: May 28, 2021Publication date: December 2, 2021Inventors: Madhusudan K. Iyengar, Christopher Malone, Woon-Seong Kwon, Emad Samadiani, Melanie Beauchemin, Padam Jain, Teckgyu Kang, Yuan Li, Connor Burgess, Norman Paul Jouppi, Nicholas Stevens-Yu, Yingying Wang
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Publication number: 20200035583Abstract: While the use of 2.5D/3D packaging technology results in a compact IC package, it also raises challenges with respect to thermal management. Integrated component packages according to the present disclosure provide a thermal management solution for 2.5D/3D IC packages that include a high-power component integrated with multiple lower-power components. The thermal solution provided by the present disclosure includes a mix of passive cooling by traditional heatsink or cold plate and active cooling by thermoelectric cooling (TEC) elements. Certain methods according to the present disclosure include controlling a temperature during normal operation in an IC package that includes a plurality of lower-power components located adjacent to a high-power component in which the high-power component generates a greater amount of heat relative to each of the lower-power components during normal operation.Type: ApplicationFiled: October 8, 2019Publication date: January 30, 2020Inventors: Melanie Beauchemin, Madhusudan Iyengar, Christopher Malone, Gregory Imwalle
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Patent number: 10504816Abstract: While the use of 2.5D/3D packaging technology results in a compact IC package, it also raises challenges with respect to thermal management. Integrated component packages according to the present disclosure provide a thermal management solution for 2.5D/3D IC packages that include a high-power component integrated with multiple lower-power components. The thermal solution provided by the present disclosure includes a mix of passive cooling by traditional heatsink or cold plate and active cooling by thermoelectric cooling (TEC) elements. Certain methods according to the present disclosure include controlling a temperature during normal operation in an IC package that includes a plurality of lower-power components located adjacent to a high-power component in which the high-power component generates a greater amount of heat relative to each of the lower-power components during normal operation.Type: GrantFiled: September 6, 2017Date of Patent: December 10, 2019Assignee: Google LLCInventors: Melanie Beauchemin, Madhusudan Iyengar, Christopher Malone, Gregory Imwalle
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Publication number: 20190074237Abstract: While the use of 2.5D/3D packaging technology results in a compact IC package, it also raises challenges with respect to thermal management. Integrated component packages according to the present disclosure provide a thermal management solution for 2.5D/3D IC packages that include a high-power component integrated with multiple lower-power components. The thermal solution provided by the present disclosure includes a mix of passive cooling by traditional heatsink or cold plate and active cooling by thermoelectric cooling (TEC) elements. Certain methods according to the present disclosure include controlling a temperature during normal operation in an IC package that includes a plurality of lower-power components located adjacent to a high-power component in which the high-power component generates a greater amount of heat relative to each of the lower-power components during normal operation.Type: ApplicationFiled: September 6, 2017Publication date: March 7, 2019Inventors: Melanie Beauchemin, Madhusudan Iyengar, Christopher Malone, Gregory Imwalle
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Patent number: 9542643Abstract: Certain aspects of the present disclosure support operating simultaneously multiple super neuron processing units in an artificial nervous system, wherein a plurality of artificial neurons is assigned to each super neuron processing unit. The super neuron processing units can be interfaced with a memory for storing and loading synaptic weights and plasticity parameters of the artificial nervous system, wherein organization of the memory allows contiguous memory access.Type: GrantFiled: May 1, 2014Date of Patent: January 10, 2017Assignee: QUALCOMM INCORPORATEDInventors: Jeffrey Alexander Levin, Venkat Rangan, Erik Christopher Malone
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Patent number: 9460384Abstract: Methods and apparatus are provided for effecting modulation using global scalar values in a spiking neural network. One example method for operating an artificial nervous system generally includes determining one or more updated values for artificial neuromodulators to be used by a plurality of entities in a neuron model and providing the updated values to the plurality of entities.Type: GrantFiled: April 23, 2014Date of Patent: October 4, 2016Assignee: QUALCOMM INCORPORATEDInventors: Jeffrey Alexander Levin, Yinyin Liu, Sarah Paige Gibson, Michael Campos, Vikram Gupta, Victor Hokkiu Chan, Edward Hanyu Liao, Erik Christopher Malone
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Patent number: 9427770Abstract: A dual washer pull plug for masking a mechanical part. The dual washer pull plug includes a first centering component and a second centering component. A first masking flange is located at a first end of the first centering component and the first centering component is configured to center the first masking flange relative to an aperture of a mechanical part on a first side of the mechanical part. A second masking flange is located at a first end of the second centering component and the second centering component is configured to center the second masking flange relative to the aperture of the mechanical part on a second side of the mechanical part.Type: GrantFiled: August 22, 2014Date of Patent: August 30, 2016Assignee: Engineered Products and Services, Inc.Inventors: Christopher Malone, Kissak Sarajian, Todd Schuh
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Patent number: 9165245Abstract: Apparatus and methods for partial evaluation of synaptic updates in neural networks. In one embodiment, a pre-synaptic unit is connected to a several post synaptic units via communication channels. Information related to a plurality of post-synaptic pulses generated by the post-synaptic units is stored by the network in response to a system event. Synaptic channel updates are performed by the network using the time intervals between a pre-synaptic pulse, which is being generated prior to the system event, and at least a portion of the plurality of the post synaptic pulses. The system event enables removal of the information related to the portion of the post-synaptic pulses from the storage device. A shared memory block within the storage device is used to store data related to post-synaptic pulses generated by different post-synaptic nodes. This configuration enables memory use optimization of post-synaptic units with different firing rates.Type: GrantFiled: May 12, 2014Date of Patent: October 20, 2015Assignee: QUALCOMM TECHNOLOGIES INC.Inventors: Eugene M. Izhikevich, Filip Piekniewski, Jayram Moorkanikara Nageswaran, Jeffrey Alexander Levin, Venkat Rangan, Erik Christopher Malone
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Patent number: 9147156Abstract: Apparatus and methods for efficient synaptic update in a network such as a spiking neural network. In one embodiment, the post-synaptic updates, in response to generation of a post-synaptic pulse by a post-synaptic unit, are delayed until a subsequent pre-synaptic pulse is received by the unit. Pre-synaptic updates are performed first following by the post-synaptic update, thus ensuring synaptic connection status is up-to-date. The delay update mechanism is used in conjunction with system “flush” events in order to ensure accurate network operation, and prevent loss of information under a variety of pre-synaptic and post-synaptic unit firing rates. A large network partition mechanism is used in one variant with network processing apparatus in order to enable processing of network signals in a limited functionality embedded hardware environment.Type: GrantFiled: September 21, 2011Date of Patent: September 29, 2015Assignee: QUALCOMM TECHNOLOGIES INC.Inventors: Eugene M. Izhikevich, Filip Piekniewski, Jayram Moorkanikara Nageswaran, Jeffrey Alexander Levin, Venkat Rangan, Erik Christopher Malone
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Publication number: 20150269480Abstract: Certain aspects of the present disclosure support a method and apparatus for implementing kortex neural network processor within an artificial nervous system. According to certain aspects, a plurality of spike events can be generated by a plurality of neuron unit processors of the artificial nervous system, and the spike events can be sent from a subset of the neuron unit processors to another subset of the neuron unit processors via a plurality of synaptic connection processors of the artificial nervous system.Type: ApplicationFiled: June 9, 2014Publication date: September 24, 2015Inventors: Jeffrey Alexander LEVIN, Erik Christopher MALONE, Edward Hanyu LIAO
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Publication number: 20150161506Abstract: Methods and apparatus are provided for effecting modulation using global scalar values in a spiking neural network. One example method for operating an artificial nervous system generally includes determining one or more updated values for artificial neuromodulators to be used by a plurality of entities in a neuron model and providing the updated values to the plurality of entities.Type: ApplicationFiled: April 23, 2014Publication date: June 11, 2015Applicant: QUALCOMM INCORPORATEDInventors: Jeffrey Alexander LEVIN, Yinyin LIU, Sarah Paige GIBSON, Michael CAMPOS, Vikram GUPTA, Victor Hokkiu CHAN, Edward Hanyu LIAO, Erik Christopher MALONE
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Publication number: 20150134582Abstract: Aspects of the present disclosure relate to methods and apparatus for training an artificial nervous system. According to certain aspects, timing of spikes of an artificial neuron during a training iteration are recorded, the spikes of the artificial neuron are replayed according to the recorded timing, during a subsequent training iteration, and parameters associated with the artificial neuron are updated based, at least in part, on the subsequent training iteration.Type: ApplicationFiled: September 24, 2014Publication date: May 14, 2015Inventors: Jeffrey Alexander LEVIN, Venkat RANGAN, Erik Christopher MALONE
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Publication number: 20150046381Abstract: Methods and apparatus are provided for implementing delays in an artificial nervous system. Synaptic and/or axonal delays between a post-synaptic artificial neuron and one or more pre-synaptic artificial neurons may be accounted for at the post-synaptic artificial neuron. One example method for managing delay between neurons in an artificial nervous system generally includes receiving, at a post-synaptic artificial neuron, input current values from one or more pre-synaptic artificial neurons; accounting for delays between the one or more pre-synaptic artificial neurons and the post-synaptic artificial neuron at the post-synaptic artificial neuron; and determining a state of the post-synaptic artificial neuron based at least in part on at least a portion of the input current values, according to the accounting.Type: ApplicationFiled: November 19, 2013Publication date: February 12, 2015Applicant: QUALCOMM IncorporatedInventors: Erik Christopher MALONE, Venkat RANGAN, Jeffrey Alexander LEVIN
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Publication number: 20140366800Abstract: A dual washer pull plug for masking a mechanical part. The dual washer pull plug includes a first centering component and a second centering component. A first masking flange is located at a first end of the first centering component and the first centering component is configured to center the first masking flange relative to an aperture of a mechanical part on a first side of the mechanical part. A second masking flange is located at a first end of the second centering component and the second centering component is configured to center the second masking flange relative to the aperture of the mechanical part on a second side of the mechanical part.Type: ApplicationFiled: August 22, 2014Publication date: December 18, 2014Inventors: Christopher Malone, Kissak Sarajian, Todd Schuh
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Publication number: 20140351190Abstract: Certain aspects of the present disclosure support operating simultaneously multiple super neuron processing units in an artificial nervous system, wherein a plurality of artificial neurons is assigned to each super neuron processing unit. The super neuron processing units can be interfaced with a memory for storing and loading synaptic weights and plasticity parameters of the artificial nervous system, wherein organization of the memory allows contiguous memory access.Type: ApplicationFiled: May 1, 2014Publication date: November 27, 2014Applicant: QUALCOMM INCORPORATEDInventors: Jeffrey Alexander LEVIN, Venkat RANGAN, Erik Christopher MALONE
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Patent number: 8826852Abstract: The present invention is an optimized DWP for minimizing coating error that has two centering components which center the DWP inside a threaded or non-threaded opening effectively masking the threads and/or opening during the coating process.Type: GrantFiled: April 12, 2010Date of Patent: September 9, 2014Assignee: Engineered Products and Services, Inc.Inventors: Christopher Malone, Kissak Sarajian, Todd Schuh