Abstract: A system for generating processor hardware supports a language for significant extensions to the processor instruction set, where the designer specifies only the semantics of the new instructions and the system generates other logic. The extension language provides for the addition of processor state, including register files, and instructions that operate on that state. The language also provides for new data types to be added to the compiler to represent the state added. It allows separate specification of reference semantics and instruction implementation, and uses this to automate design verification. In addition, the system generates formatted instruction set documentation from the language specification.

Abstract: A system for generating processor hardware supports a language for significant extensions to the processor instruction set, where the designer specifies only the semantics of the new instructions and the system generates other logic. The extension language provides for the addition of processor state, including register files, and instructions that operate on that state. The language also provides for new data types to be added to the compiler to represent the state added. It allows separate specification of reference semantics and instruction implementation, and uses this to automate design verification. In addition, the system generates formatted instruction set documentation from the language specification.

Abstract: A system for generating processor hardware supports a language for significant extensions to the processor instruction set, where the designer specifies only the semantics of the new instructions and the system generates other logic. The extension language provides for the addition of processor state, including register files, and instructions that operate on that state. The language also provides for new data types to be added to the compiler to represent the state added. It allows separate specification of reference semantics and instruction implementation, and uses this to automate design verification. In addition, the system generates formatted instruction set documentation from the language specification.

Abstract: A system for generating processor hardware supports a language for significant extensions to the processor instruction set, where the designer specifies only the semantics of the new instructions and the system generates other logic. The extension language provides for the addition of processor state, including register files, and instructions that operate on that state. The language also provides for new data types to be added to the compiler to represent the state added. It allows separate specification of reference semantics and instruction implementation, and uses this to automate design verification. In addition, the system generates formatted instruction set documentation from the language specification.

Abstract: A system for generating processor hardware supports a language for significant extensions to the processor instruction set, where the designer specifies only the semantics of the new instructions and the system generates other logic. The extension language provides for the addition of processor state, including register files, and instructions that operate on that state. The language also provides for new data types to be added to the compiler to represent the state added. It allows separate specification of reference semantics and instruction implementation, and uses this to automate design verification. In addition, the system generates formatted instruction set documentation from the language specification.

Abstract: A system for generating processor hardware supports a language for significant extensions to the processor instruction set, where the designer specifies only the semantics of the new instructions and the system generates other logic. The extension language provides for the addition of processor state, including register files, and instructions that operate on that state. The language also provides for new data types to be added to the compiler to represent the state added. It allows separate specification of reference semantics and instruction implementation, and uses this to automate design verification. In addition, the system generates formatted instruction set documentation from the language specification.

Abstract: A hardware abstraction layer operates as a system architectural layer between a real-time operating system and an underlying configurable processor. The hardware abstraction layer provides an abstraction of processor-specific functionality to the operating system. In particular, it abstracts configurable processor features visible to the operating system to provide a uniform, standardized interface between the operating system and the configurable processor on which it runs. Thus, an operating system running on top of the hardware abstraction layer will work on all configurations of the processor which differ from one another only in the configuration parameters covered by the hardware abstraction layer. The hardware abstraction layer may be generated using the same information that is used to describe the features being configured in the configurable processor.

Abstract: An improved printer is provided which includes a separate hardware compression module and hardware decompression module contained within the ASIC of the print engine. A "Request Counter" register is decremented each time memory is requested to store a block of bitmap image data. When the Request Counter decreases to a predetermined value, the current size of the remaining "free memory" space is evaluated. If this free memory is less than another predetermined value (a "low water mark"), then blocks of data that have already been stored in the printer's memory are sent to the compression module to be compressed before the printer literally runs out of free memory, and the printer can continue storing and processing more incoming print job data. By thus preserving some of the free memory, the printer can continue to process or rasterize more print data while the compression hardware simultaneously operates independently to compress one or more blocks of data.

Abstract: An improved networked system having a host computer and multiple printers is provided in which the printers have a bi-directional data communications capability and have at least one memory device capable of storing print data and other types of data files. The host computer can be utilized by a user or a Network Administrator to "read" the contents of each memory device on each printer connected to the network that has the NPAP bi-directional communications capability. The user/Network Administrator can de-fragment data files (e.g., print job files) on a flash RAM memory device, or can format one of the memory devices of a printer (which deletes all of the files stored on that memory device). Furthermore, the user/Network Administrator can transfer a file from the memory of one of the printers on the network to the memory of a second of the printers on the network.

Abstract: An improved printer is provided that improves the response time before jobs are printer by providing a "fast data path" for certain print jobs while also storing on a hard disk all incoming print job data. This "fast data path" is especially useful in situations where the incoming print job lacks an "end of file" code, which could otherwise hold up the processing of either this print job or later print jobs. Once the printer becomes relatively busy, and begins to accumulate a "queue" of print jobs waiting to be processed and printed, the printer will automatically store all of the print job data on the non-volatile memory (e.g., a hard disk) before that same data is sent to the processing circuitry.

Abstract: Printer (1) has code in memory (5) to interpret one or more page description languages and also stores in memory (5) a table of routines useful in other interpreters and their addresses, as well as code to link partially compiled object code in response to directions in Relocation Tables in the partially compiled code. Data is downloaded to the printer by cable (23) to add another interpreter to the printer. That data is employed by the linking code, which responds to the directions in the Relocation Tables to complete the new interpreter making use of routines already stored in the printer. Since the stored routine table is lengthy, it is compressed. The routine table may be downloaded rather than permanently stored.

Abstract: An improved networked system having a host computer and multiple printers is provided in which the printers have a bi-directional data communications capability and have at least one memory device capable of storing print data and other types of data files. The host computer can be utilized by a user or a Network Administrator to "read" the contents of each memory device on each printer connected to the network that has the NPAP bi-directional communications capability. The user/Network Administrator can transfer a file from the memory of one of the printers on the network to the memory of a second of the printers on the network. When a given resource management function has been completed, an updated resource directory is automatically displayed at the host which includes all of the changes resulting from the earlier resource management function command.

Abstract: To process bit maps for full color and other data-intense bit maps for printing, a data processing routine (FIG. 4) determines if a block at data within a page is not in color or is otherwise in a single value. Such data is stored in DRAM (28) in one bit per pel form. Other blocks are stored with eight bit for each pel. A table is then developed defining the contiguous order in a page (FIG. 6). An ASIC (32) then transfers the pel information in order of printing to a video RAM (40) with the eight bits restored for data stored in one bit per pel form. The data applied to that ASIC is decompressed.