Abstract: Data processing logic (10) is fabricated on an integrated circuit device and is outputted to a plurality of output pins (1-N). A number of these pins (34, 36, 38) which are normally function outputs, and a reset pin (24), are used to invoke a test state on the integrated circuit device. Test control logic generates two test flags (TA, TB) in response to test signals on two of these pins (34, 36). These two test flags are decoded (14, 18, 20, 22) to control all signal output pins (1-N) from the integrated circuit device by forcing a high-level, low-level, or high-impedance condition, as selected by external stimulus at the output pins, regardless of the condition of the internal circuitry on the integrated circuit device. A test flag TC (60) is generated in response to a test signal on pin (38). This TC flag is used to signal the data processing logic (10) to initiate a functional self-check operation.