Patents by Inventor Christopher McCall

Christopher McCall has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 12060174
    Abstract: A storage case, including, at least one door which is moveable between a first position in which the door is closed and a second position in which the door is opened; a platform, which can support an aerial vehicle; and a mechanical connection means which is connected between the platform and the at least one door, wherein the mechanical connection means is configured such that as the door is moved from its first position to its second position the platform is simultaneously elevated; and as the door is moved from its second position to its first position the platform is simultaneously lowered; and a controller configured to control the mechanical connection means. There is further provided a corresponding method of deploying an aerial vehicle; a corresponding method of storing an aerial vehicle; an assembly including the storage case and an aerial vehicle; and a vehicle including the storage case.
    Type: Grant
    Filed: May 10, 2021
    Date of Patent: August 13, 2024
    Assignee: FOTOKITE AG
    Inventors: Victor Chub, Alex Lieber, Sergei Lupashin, Christopher McCall, Milan Rohrer, Lukas Scherrer, Alexander Zhitelzeyf
  • Publication number: 20230202692
    Abstract: A storage case, including, at least one door which is moveable between a first position in which the door is closed and a second position in which the door is opened; a platform, which can support an aerial vehicle; and a mechanical connection means which is connected between the platform and the at least one door, wherein the mechanical connection means is configured such that as the door is moved from its first position to its second position the platform is simultaneously elevated; and as the door is moved from its second position to its first position the platform is simultaneously lowered; and a controller configured to control the mechanical connection means. There is further provided a corresponding method of deploying an aerial vehicle; a corresponding method of storing an aerial vehicle; an assembly including the storage case and an aerial vehicle; and a vehicle including the storage case.
    Type: Application
    Filed: May 10, 2021
    Publication date: June 29, 2023
    Inventors: Victor Chub, Alex Lieber, Sergei Lupashin, Christopher McCall, Milan Rohrer, Lukas Scherrer, Alexander Zhitelzeyf
  • Patent number: 6785826
    Abstract: A method and apparatus for reducing power dissipation within a functional unit of a microprocessor includes a power sensing circuit for sensing power dissipation of the functional unit. A low power mode identifying circuit identifies when the measured power dissipation of the functional unit exceeds a predetermined amount or value. Upon such a condition, a low power mode circuit operates the functional unit in a low power mode thereby reducing its power dissipation. Operation of the functional unit in the low power mode continues until the power dissipation reaches a safe level. The functional unit internally determines power dissipation and selectively enters a low power mode to reduce power dissipation of the functional unit. Low power mode operation of the functional unit reduces power dissipation of the functional unit.
    Type: Grant
    Filed: July 17, 1996
    Date of Patent: August 31, 2004
    Assignee: International Business Machines Corporation
    Inventors: Christopher McCall Durham, Peter Juergen Klim
  • Patent number: 6654937
    Abstract: A method and apparatus is provided for enabling a static timing tool to analyze and test register files in integrated circuits to find correct paths and ignore detected contention. This is achieved by utilizing pattern matching in the static timing tool and having the tool perform certain operations on the transistors of the pattern matched. The methodology includes considering the write word lines as clock nodes, disabling signal propagation through the memory element components, forcing predetermined internal nodes to be of inverse polarity, establishing signal direction through the circuit elements, and indicating that one or more of the predetermined nodes are not to be reported.
    Type: Grant
    Filed: August 10, 2000
    Date of Patent: November 25, 2003
    Assignee: International Business Machines Corporation
    Inventors: Matthew J. Amatangelo, Christopher McCall Durham, Peter Juergen Klim
  • Patent number: 6577152
    Abstract: A noise suppression circuit for suppressing above-ground noise is disclosed. The noise suppression circuit for suppressing noises includes a first inverter, a second inverter, and a one-shot circuit. The first inverter, connected to an input line, switches at a first voltage value above which a noise-coupling event is suspected. The second inverter, also connected to the input line, switches at a second voltage value above which a full-switch input is assumed. A first transistor is coupled to the input line. A second transistor passes an output of the second inverter to a gate of the first transistor when an output of the one-shot circuit is high. The third transistor holds the gate of the first transistor low when the output of the one-shot circuit is low.
    Type: Grant
    Filed: May 28, 1999
    Date of Patent: June 10, 2003
    Assignee: International Business Machines Corporation
    Inventors: Christopher McCall Durham, Peter Juergen Klim
  • Patent number: 6532574
    Abstract: Adjacent signal lines within the critical path of logic within an integrated circuit are checked for capacitive coupling induced signal delay variations resulting from concurrent signal transitions. When found, signal transition overlap is eliminated by delaying the clock edge (rising or falling) triggering the signal driving logic, without necessarily delaying the other clock edge. A delay circuit is incorporated into clock stages for the signal driving logic, and may be selectively actuated to delay the clock edge to particular signal driving logic circuits. Selection of signal lines in which signal transitions are to be delayed may be performed after manufacture of the integrated circuit, and iterative determinations may be required since signal adjustment may create new critical paths within the integrated circuit logic.
    Type: Grant
    Filed: August 17, 2000
    Date of Patent: March 11, 2003
    Assignee: International Business Machines Corporation
    Inventors: Christopher McCall Durham, Sharad Mehrotra, Alexander Koos Spencer, Barry Duane Williamson
  • Patent number: 6522170
    Abstract: A Self-Timed CMOS Static Circuit Technique has been invented that provides full handshaking to the source circuits; prevention of input data loss by virtue off interlocking both internal and incoming signals; full handshaking between the circuit and sink self-timed circuitry; prevention of lost access operation information by virtue of an internal lock-out for the output data information; and plug-in compatibility for some classes of dynamic self-timed systems. The net result of the overall system is that static CMOS circuits can now be used to generate a self-timed system. This is in contrast to existing self-timed systems that rely on dynamic circuits. Thus, the qualities of the static circuitry can be preserved and utilized to their fullest advantage.
    Type: Grant
    Filed: April 27, 1998
    Date of Patent: February 18, 2003
    Assignee: International Business Machines Corporation
    Inventors: Christopher McCall Durham, Peter Juergen Klim
  • Patent number: 6507929
    Abstract: A system within a complementary logic circuit having a true tree and a complement tree, for correcting an illegal non-complementary output caused by a defect in either tree. A complementary logic circuit has a true tree for producing a true signal and a complement tree for producing a complement signal. The true signal is utilized to generate a true output signal from the complementary logic circuit and the complement signal is utilized to generate a complement output signal from the complementary logic circuit. Multiplexing means within the true and complement trees are utilized to selectively replace the true (complement) signal with the complement (true) signal within the true (complement) tree, such that the complement (true) tree is utilized to correct the occurrence of a proscribed non-complementary condition at the output of the complementary logic circuit to diagnose a defect during diagnostic testing or to override a defect during normal runtime operation.
    Type: Grant
    Filed: March 15, 1999
    Date of Patent: January 14, 2003
    Assignee: International Business Machines Corporation
    Inventors: Christopher McCall Durham, Peter Juergen Klim, Ronald Gene Walther
  • Patent number: 6502220
    Abstract: A system and method for detecting and rectifying a proscribed non-complementary output from a complementary logic circuit. A complementary logic circuit having a true tree and a complement tree is provided. The true tree produces a true signal utilized to generate a true output signal from the complementary logic circuit. The complement tree produces a complement signal utilized to generate a complement output signal from the complementary logic circuit. Logic means coupled to the output of the complementary logic circuit detect an occurrence of a non-complementary output from the complementary logic circuit. Multiplexing means within the true tree is utilized to selectively replace the true signal with the complement signal within the true tree in response to detection by the logic means of a non-complementary output, such that a non-complementary output is seamlessly detected and rectified.
    Type: Grant
    Filed: March 15, 1999
    Date of Patent: December 31, 2002
    Assignee: International Businesss Machines Corporation
    Inventors: Christopher McCall Durham, Peter Juergen Klim
  • Patent number: 6406980
    Abstract: A wafer design layout and method of producing multiple integrated chip types using a single set of masks for a wafer and then at the time the type of chip desired is known, using a few customizing steps to produce the final integrated chip is provided. In one embodiment, the wafer layout includes a plurality of groupings of components and a plurality of dicing channels separating each of the components from others of the components. After the particular type of integrated circuit chip desired is selected, the wafer may then have the final few layers processed and the chips removed using the appropriate dicing channels for the integrated circuit chip desired.
    Type: Grant
    Filed: August 24, 2000
    Date of Patent: June 18, 2002
    Assignee: International Business Machines Corporation
    Inventors: Matthew J. Amatangelo, Christopher McCall Durham, Peter Juergen Klim, Stephen Larry Runyon
  • Patent number: 6285217
    Abstract: Dynamic logic circuits with reduced evaluation time provide faster output in dynamically evaluating logic circuits by increasing the rate of change of the voltage at the junction of logic input ladders. The circuits use a cross-coupled amplifier to charge the input ladder combining node once the node begins to evaluate.
    Type: Grant
    Filed: September 8, 1999
    Date of Patent: September 4, 2001
    Assignee: International Business Machines Corporation
    Inventors: Christopher McCall Durham, Peter Juergen Klim, Younes Lofti, John Beck
  • Patent number: 6269045
    Abstract: A circuit evaluates a plurality of data inputs, provides for stabilization of the evaluation, and then drives the evaluation from the circuit. The providing of the stabilization is performed by delaying an activation signal, which controls the evaluation circuitry. The activation signal may be either a clock signal or a reset signal. This circuit may be an address decoder that decodes certain ones of the address signals during the evaluation phase, and then drives the evaluation during the second phase.
    Type: Grant
    Filed: February 8, 2000
    Date of Patent: July 31, 2001
    Assignee: International Business Machines Corporation
    Inventors: Christopher McCall Durham, Peter Juergen Klim, Roy Keith Waite
  • Patent number: 6252418
    Abstract: A noise suppression circuit for suppressing noises above and below reference voltages is provided. The noise suppression circuit for suppressing noises includes a clamping transistor, a feedback circuit, and a presetting means for presetting an internal latch of the noise suppression circuit to a predetermined state. The predetermined state is a high state or a low state depending upon the type of noise suppression accomplished by the circuit. After the occurrence of a noise coupling event, the clamping transistor restores the state of a data input of a circuit to which the suppression circuit is providing protection. The feedback circuit then turns off the clamping transistor after a predetermined amount of time.
    Type: Grant
    Filed: September 23, 1999
    Date of Patent: June 26, 2001
    Assignee: International Business Machines Corporation
    Inventors: Christopher McCall Durham, Peter Juergen Klim, Shon Alan Schmidt
  • Patent number: 6253350
    Abstract: A method and system for detecting faults within dual-rail complementary logic circuits. A method and system are disclosed for detecting faults within dual-rail complementary logic circuits. A dual-rail complementary logic circuit is coupled to an associated complementary fault detection circuit within an integrated circuit. Thereafter, the presence of a non-complementary logic signal can be detected at an output of the complementary fault detection circuit, in response to providing an input signal at an input of the dual-rail complementary logic circuit, such that the presence of a non-complementary logic signal at an output of the complementary fault detection circuit indicates the presence of a fault within the associated complementary logic circuit.
    Type: Grant
    Filed: July 9, 1998
    Date of Patent: June 26, 2001
    Assignee: International Business Machines Corporation
    Inventors: Christopher McCall Durham, Peter Juergen Klim, Ronald Gene Walther
  • Patent number: 6240489
    Abstract: A method for implementing a pseudo least recent used mechanism in a four-way cache memory within a data processing system is disclosed. Within a four-way set associative cache memory, each congruence class contains four cache lines. Each congruence class within the cache memory is associated to a least recently used (LRU) field that has four bits. Each of four cache lines within the congruence class is then assigned with a respective set number. The set number of a cache line designated as a least recently used set among the four cache lines is stored in two bits of the LRU field. The set number of a cache line designated as a most recently used set among the four cache lines is stored in another two bits of the LRU field. In response to a determination that the set number of the least recently used set is higher than the set number of the most recently used set, one of the remaining two cache lines that has a higher set number is assigned to be a second least recently used set.
    Type: Grant
    Filed: February 24, 1999
    Date of Patent: May 29, 2001
    Assignee: International Business Machines Corporation
    Inventors: Christopher McCall Durham, Brian Patrick Hanley
  • Patent number: 6208907
    Abstract: A method and apparatus is provided for enabling the transformation of a domino circuit to a static circuit without requiring the re-design of the chip or integrated circuit mask set. The domino circuit masks may be designed to include additional unconnected devices as appropriate which may be added or connected into the circuit after chip design release by changing only interconnection masks. Spare devices can be added and selectively used to make a domino circuit metal-mask programmable into a logically equivalent static circuit. In a first exemplary method, extra devices are added to, and/or existing devices are re-wired in the domino circuitry to make a complementary equivalent static gate. In a second exemplary methodology, the domino circuit is converted into a pseudo-NMOS circuit using devices already available in the circuit and modifying the circuit connections thereto.
    Type: Grant
    Filed: January 30, 1998
    Date of Patent: March 27, 2001
    Assignee: International Business Machines Corporation
    Inventors: Christopher McCall Durham, Visweswara Rao Kodali, Douglas Ele Martin, Harsh Dev Sharma
  • Patent number: 6209055
    Abstract: For transmitting information on a plurality of integrated circuit conductive lines, n conductive lines are provided on a path in an integrated circuit. The path has first and second portions, and an interposing, transition portion. The lines have first positions with respect to one another in the first portion, and certain of the lines change relative positions in the transition portion, so that the lines have second positions with respect to one another in the second portion. The information is encoded in a format wherein no more than one of the n lines has a signal asserted thereon at a time, so that there is a reduction in noise induced among the lines.
    Type: Grant
    Filed: October 29, 1998
    Date of Patent: March 27, 2001
    Assignee: International Business Machines Corporation
    Inventors: Christopher McCall Durham, Peter Juergen Klim, John Andrew Beck
  • Patent number: 6195308
    Abstract: A circuit evaluates a plurality of data inputs, provides for stabilization of the evaluation, and then drives the evaluation from the circuit. The providing of the stabilization is performed by delaying an activation signal, which controls the evaluation circuitry. The activation signal may be either a clock signal or a reset signal. This circuit may be an address decoder that decodes certain ones of the address signals during the evaluation phase, and then drives the evaluation during the second phase.
    Type: Grant
    Filed: February 8, 2000
    Date of Patent: February 27, 2001
    Assignee: International Business Machines Corporation
    Inventors: Christopher McCall Durham, Peter Juergen Klim, Roy Keith Waite
  • Patent number: 6189133
    Abstract: False transitions resulting from capacitive coupling between parallel interconnects driven by dynamic circuits are reduced by classifying interconnects based on the timing of expected data transitions in the signals they carry. Interconnects carrying signals expected to transition during a first portion of a processor cycle are treated as one category, while interconnects carrying signals expected to transition during a second, different portion of the processors cycle are treated as a second category. Interconnects of different categories are interdigitated, a resets of dynamic driving circuits are tuned so that, at any given time, alternate interconnects are “quiet” or stable. Therefore interconnects being driven with data transitions are directly adjacent to quiet lines, and foot devices are implemented as necessary to prevent coupling expected during the reset phase.
    Type: Grant
    Filed: May 14, 1998
    Date of Patent: February 13, 2001
    Assignees: International Business Machines Corporation, Motorola, Inc.
    Inventors: Christopher McCall Durham, Marlin Wayne Frederick, Jr., Peter Juergen Klim, James Edward Dunning
  • Patent number: D948210
    Type: Grant
    Filed: May 19, 2020
    Date of Patent: April 12, 2022
    Inventors: Milan Rohrer, Victor Chub, Lukas Scherrer, Sergei Lupashin, Alex Lieber, Christopher McCall