Abstract: A method for back-off retry with priority routing includes routing a data transfer between an input of a single, cohesive SAS expander and an output of the SAS expander via at least one inter-expander link (IEL), the expander including a first SAS expander and at least one additional SAS expander. The method includes routing a first OPEN request on a direct path through the first SAS expander to a port of a device and routing a second OPEN request on an alternate path from the first SAS expander and through a second SAS expander to the port of the device. The method further includes, upon determination of a failed link or a busy link, re-routing the data transfer from the second SAS expander to the first SAS expander or a third SAS expander, or retrying the data transfer through the second SAS expander.

Abstract: A method for back-off retry with priority routing in a single, cohesive SAS expander includes routing a data transfer between an input of a single, cohesive SAS expander and an output of the single, cohesive SAS expander, wherein the single, cohesive expander includes a first SAS expander, and at least one additional SAS expander via at least one inter-expander link (IEL). The routing of data may further include routing a first OPEN request on a direct path through the first SAS expander to a port of a device and routing a second OPEN request on an alternate path from the first SAS expander and through a second SAS expander to the port of the device. The method further includes determining link availability between the second SAS expander and the port of the device, and, upon determination of a failed link or a busy link, re-routing the data transfer from the second SAS expander to the first SAS expander or a third SAS expander, or retrying the data transfer through the second SAS expander.

Abstract: A first SAS expander including at least phys is operably coupled to a first and a second SAS wide port. A second SAS expander including at least two phys is operably coupled to the first and the second SAS wide port. The first and the second SAS wide port each include at least two lanes, one of each at least two lanes designateable as a connection request lane. The connection request lane of each SAS wide port is operably coupled to a different SAS expander.

Abstract: A failed link is detected between a first SAS expander and a device. A data transfer of the first SAS expander connected to the device via the failed link is re-routed to a second SAS expander connected to the device via a functional link. The first SAS expander is connected to the SAS expander via the phys of the first SAS expander and the phys of the second SAS expander for inter-expander communications.

Abstract: A method for back-off retry with priority routing in a single, cohesive SAS expander includes routing a data transfer between an input of a single, cohesive SAS expander and an output of the single, cohesive SAS expander, wherein the single, cohesive expander includes a first SAS expander, and at least one additional SAS expander via at least one inter-expander link (IEL). The routing of data may further include routing a first OPEN request on a direct path through the first SAS expander to a port of a device and routing a second OPEN request on an alternate path from the first SAS expander and through a second SAS expander to the port of the device. The method further includes determining link availability between the second SAS expander and the port of the device, and, upon determination of a failed link or a busy link, re-routing the data transfer from the second SAS expander to the first SAS expander or a third SAS expander, or retrying the data transfer through the second SAS expander.

Abstract: The optimal lanes of at least one SAS wide port for the data connection are discovered. The allowable lanes for the data connection within the SAS wide ports of each level of the SAS domain are specified. The specified allowable lanes for the data connection are checked. The data connection is created on the specified allowable lanes.

Abstract: A first SAS expander including at least two phys is operably coupled to a first and a second SAS wide port. A second SAS expander including at least two phys is operably coupled to the first and the second SAS wide port. The first and the second SAS wide port each include at least two lanes, one of each at least two lanes designateable as a connection request lane. The connection request lane of each SAS wide port is operably coupled to a different SAS expander.

Abstract: The optimal lanes of at least one SAS wide port for the data connection are discovered. The allowable lanes for the data connection within the SAS wide ports of each level of the SAS domain are specified. The specified allowable lanes for the data connection are checked. The data connection is created on the specified allowable lanes.

Abstract: A failed link is detected between a first SAS expander and a device. A data transfer of the first SAS expander connected to the device via the failed link is re-routed to a second SAS expander connected to the device via a functional link. The first SAS expander is connected to the SAS expander via the phys of the first SAS expander and the phys of the second SAS expander for inter-expander communications.

Abstract: The present invention relates to a method, circuit, and system for performing write journal operations on a bus interface controller board or bus interface controller integrated circuit chip. This is achieved by placed a write journal memory on the board or chip and supplying power to it from an external power source. Preferably, the external power source is a battery. The internal memory may use bus interface controller power when available to prolong battery life.

Abstract: A computer system motherboard includes connection points for receiving a processor and a disk controller card. At least one communication bus connects the processor and the disk controller card. Another connection point is provided between the processor and the disk controller card for receiving one of a jumper or a card that includes RAID controller circuitry. The processor executes a device discovery process and selectively loads RAID device drivers in response to the discovery of a card that includes RAID controller circuitry.

Abstract: The present invention relates to a method, circuit, and system for performing write journal operations on a bus interface controller board or bus interface controller integrated circuit chip. This is achieved by placed a write journal memory on the board or chip and supplying power to it from an external power source. Preferably, the external power source is a battery. The internal memory may use bus interface controller power when available to prolong battery life.