Abstract: A system, method, and apparatus are provided to facilitate data structures for a datatype engine and provide inline compaction. The system receives, by a network interface card (NIC), a command to read data from a host memory, wherein the command indicates a datatype. The system generates a plurality of read requests comprising offsets from a base address and corresponding lengths based on the datatype. The system issues the plurality of read requests to the host memory to obtain the data from the host memory. The system obtains a byte-mask descriptor corresponding to the datatype. The system performs, based on the obtained data and the byte-mask descriptor, on-the-fly compaction of the obtained data, thereby allowing the NIC to return a requested subset of the obtained data.

Abstract: Systems and methods are provided for implementing forward error correction (FEC) on data transferred on a data link on the physical layer. Binary encoding can be done in accordance with a physical unit (phit) FEC format. The phit FEC format allows for correction of two bit errors and comprises a codeword having a variable bit size. Pre-coding the phit enables burst errors associated with the link to converted into bit errors. The data can be transmitted in the phit FEC format to a receiving PHY. The correctable two bit errors at one or more locations within the phit FEC format can then be corrected by decoding at the receiving PHY in accordance with the phit FEC. The FEC techniques can minimize latency in the PHY.

Abstract: One embodiment of the present invention provides a switch. During operation, the switch maintains a first counter to indicate a first number of packets in a queue of the switch. The switch then determines whether a clock of the switch has reached a threshold value. If the clock reaches the threshold value, the switch starts maintaining a second counter to indicate a second number of packets in the queue that have been received after the clock has reached the threshold value. The switch continues to decrement the first counter in response to a packet leaving the queue until the first counter reaches a value of zero. When the clock reaches a maximum value supported by the clock, the switch drops a third number of packets from the queue indicated by the first counter.

Abstract: Systems and methods are provided for implementing forward error correction (FEC) on data transferred on a data link on the physical layer. Binary encoding can be done in accordance with a physical unit (phit) FEC format. The phit FEC format allows for correction of two bit errors and comprises a codeword having a variable bit size. Pre-coding the phit enables burst errors associated with the link to converted into bit errors. The data can be transmitted in the phit FEC format to a receiving PHY. The correctable two bit errors at one or more locations within the phit FEC format can then be corrected by decoding at the receiving PHY in accordance with the phit FEC. The FEC techniques minimize latency in the PHY, being optimal for Gen-Z systems. The FEC techniques can provide improvements over existing FEC schemes that employ large code word sizes and experience high latency.

Abstract: One embodiment of the present invention provides a switch. During operation, the switch maintains a first counter to indicate a first number of packets in a queue of the switch. The switch then determines whether a clock of the switch has reached a threshold value. If the clock reaches the threshold value, the switch starts maintaining a second counter to indicate a second number of packets in the queue that have been received after the clock has reached the threshold value. The switch continues to decrement the first counter in response to a packet leaving the queue until the first counter reaches a value of zero. When the clock reaches a maximum value supported by the clock, the switch drops a third number of packets from the queue indicated by the first counter.

Abstract: In one example, a controller for managing a set of resources. A first structure has a first entry statically associated with one of the resources. A second structure has a second entry dynamically associative with one of the resources. A resource sharing mechanism borrows for the second structure an idle resource associated with the first structure.

Abstract: In one example, a controller for managing a set of resources. A first structure has a first entry statically associated with one of the resources. A second structure has a second entry dynamically associative with one of the resources. A resource sharing mechanism borrows for the second structure an idle resource associated with the first structure.

Abstract: A method for detecting a persistent error in a digital memory is provided. Error location information for errors detected in the digital memory is received. A group of the errors that are associated with a same error position is identified from the error location information. A number of the errors of the group that are associated with a same area of the digital memory is identified. A persistent error is determined based upon the number of the errors of the group.

Abstract: Systems and methods for mitigating latency associated with error detection and correction of a data structure are disclosed. One embodiment of a system may comprise a packet generator that builds a response packet associated with a request for a data structure based on a tag portion of the data structure. The system may also comprise an error detection and correction (EDC) component that detects and corrects errors in the data structure concurrently with the building of the response packet by the packet generator.