Abstract: A processing apparatus includes a network of interconnected processors comprising a plurality of signal processors for digitally processing input signals in real time to generate output signals and one or more control processors, each control processor controlling the operation of a plurality of signal processors. The processing apparatus automatically schedules control tasks in a plurality of time slices, where more than one control processor is provided for coordination between control processors, a wired-OR configuration connection can be provided to synchronise the beginning and/or end of the time slices. A control processor can change an address field of microcode instructions of a signal processor for implementing a multiplexer function. A control delay list can be provided for scheduling control task delays.

Abstract: This invention relates to the allocation of object code in multi-processor systems. In particular, techniques are disclosed for efficiently allocating signal processing instructions to a large array of parallel signal processing units.

Abstract: This invention relates to the allocation of object code in multi-processor systems. In particular, techniques are disclosed for efficiently allocating signal processing instructions to a large array of parallel signal processing units.

Abstract: This invention relates to the allocation of object code in multi-processor systems. In particular, techniques are disclosed for efficiently allocating signal processing instructions to a large array of parallel signal processing units.

Abstract: Data storage apparatus comprises: a memory having a plurality of addressable memory locations for storage of data items and memory address input means for receiving addresses of locations to be accessed; main input means for receiving an input address corresponding to a memory location; a counter for changing a count in response to a clock signal; address adjustment means for combining the count with an input address to generate an adjusted address corresponding to a memory location and supplying the adjusted address to the memory address input means; and means for accessing the memory location at the address supplied to the memory address input means. Also provided is a data storage method, and data processing systems including the data storage systems.