Abstract: A low semiconductor area impact mechanism for patching operations stored in a boot memory area is provided, thereby providing flexibility to such code. In this manner, current flash memory manager SCRAM, which is used for memory operations when the flash memory is unavailable can be replaced with a significantly smaller register area (e.g., a flip flop array) that provides a small patch space, variable storage, and stack. Embodiments provide such space saving without modification to the CPU core, but instead focus on the external flash memory manager. Patch code can be copied into a designated register space. Since such code used during flash memory inaccessibility is typically small, patching is provided for just a small area of the possible flash memory map, and program flow is controlled by presenting the CPU core's own address to redirect the program counter to the patch area.

Abstract: Methods and systems are disclosed for digital control for regulation of program voltages for non-volatile memory (NVM) systems. The disclosed embodiments dynamically adjust program voltages based upon parameters associated with the cells to be programmed in order to account for IR (current-resistance) voltage drops that occur within program voltage distribution lines. Other voltage variations can also be accounted for with these dynamic adjustments, as well. The parameters for cells to be programmed can include, for example, cell address locations for the cells to be programmed, the number of cells to be programmed, and/or other desired parameters associated with the cells to be programmed. The disclosed embodiments use digital control values obtained from lookup tables based upon the cell parameters to adjust output voltages generated by voltage generation circuit blocks used to program the selected cells thereby tuning the program output voltage level to a predetermined desired level.

Abstract: Methods and systems are disclosed for digital control for regulation of program voltages for non-volatile memory (NVM) systems. The disclosed embodiments dynamically adjust program voltages based upon parameters associated with the cells to be programmed in order to account for IR (current-resistance) voltage drops that occur within program voltage distribution lines. Other voltage variations can also be accounted for with these dynamic adjustments, as well. The parameters for cells to be programmed can include, for example, cell address locations for the cells to be programmed, the number of cells to be programmed, and/or other desired parameters associated with the cells to be programmed. The disclosed embodiments use digital control values obtained from lookup tables based upon the cell parameters to adjust output voltages generated by voltage generation circuit blocks used to program the selected cells thereby tuning the program output voltage level to a predetermined desired level.

Abstract: A low semiconductor area impact mechanism for patching operations stored in a boot memory area is provided, thereby providing flexibility to such code. In this manner, current flash memory manager SCRAM, which is used for memory operations when the flash memory is unavailable (e.g., high voltage operations) can be replaced with a significantly smaller register area (e.g., a flip flop array) that provides a small patch space, variable storage, and stack. Embodiments provide such space saving without modification to the CPU core, but instead focus on the external flash memory manager. Patch code can be copied into a designated register space. Since such code used during flash memory inaccessibility is typically small, patching can be provided for just a small area of the possible flash memory map, and program flow can be controlled by presenting the CPU core's own address to redirect the program counter to the patch area.

Abstract: The text is generated from voice input that divides the processing of each spoken word into a dictation event and a text event. Each dictation event handles the processing of data relating to the input into the system, and each text event deals with the generation of text from the inputted voice signals. In order to easily distinguish the dictation events from each other and text events from each other the system and method creates a data structure for storing certain information relating to each individual event. Such data structures enable the system and method to process both simple spoken words as well as spoken commands and to provide the necessary text generation in response to the spoken words or to execute an appropriate function in response to a command.

Abstract: Disclosed is a system and method for generating text from a voice input that divides the processing of each speech event into a dictation event and a text event. Each dictation event handles the processing of data relating to the input into the system, and each text event deals with the generation of text from the inputted voice signals. In order to easily distinguish the dictation events from each other and text events from each other the system and method creates a data structure for storing certain information relating to each individual event. Such data structures enable the system and method to process both simple spoken words as well as spoken commands and to provide the necessary text generation in response to the spoken words or to execute an appropriate function in response to a command. Speech recognition includes the ability to distinguish between dictation text and commands.

Abstract: A random access memory (RAM) circuit is provided wherein an input signal matrix forming an identifiable original pattern is learned and stored such that a distorted facsimile thereof may be applied to generate an output signal matrix forming a replication of the original pattern having improved recognizable features over the distorted facsimile. The input signal matrix is logically divided into a plurality of predetermined subsets comprising a unique element of the input signal matrix and the elements in the neighborhood thereof. Each predetermined subset is quantized into a first digital address and applied at the address inputs of a memory circuit for retrieving data stored in the addressed memory location, while one signal of the predetermined subset is digitized and weighted and combined with the data retrieved from the addressed memory location for storage in the same addressed memory location.