Abstract: An apparatus includes a processing circuit and a storage device. The processing circuit is configured to perform one or more processing operations in response to one or more instructions to generate an anchored-data element. The storage device is configured to store the anchored-data element. A format of the anchored-data element includes an identification item, an overlap item, and a data item. The data item is configured to hold a data value of the anchored-data element. The identification item indicates an anchor value for the data value or one or more special values.

Abstract: Briefly, example methods, apparatuses, and/or articles of manufacture are disclosed that may be implemented, in whole or in part, using one or more computing devices to facilitate and/or support one or more operations and/or techniques for creating and/or enhancing hardware obscurity via one or more randomization points, such as implemented in connection with one or more computing and/or communication networks and/or protocols.

Abstract: Briefly, example methods, apparatuses, and/or articles of manufacture are disclosed that may be implemented, in whole or in part, using one or more computing devices to facilitate and/or support one or more operations and/or techniques for an autonomous pseudo-random seed generator (APRSG) for embedded computing devices, which may include IoT-type devices, such as implemented in connection with one or more computing and/or communication networks and/or protocols.

Abstract: Various implementations described herein are directed to providing time-dependent authentication of a sending device. A message to a designated receiver is prepared. A portion of at least one secret identifier value of the sending device is retrieved. A portion of time information is retrieved. An authentication field is produced using the portion of the at least one secret identifier value and the portion of the time information. The authentication field is attached to the message. The message is transmitted to the designated receiver.

Abstract: A computing device incorporating repetitive side channel attack (SCA) countermeasures can include a timer circuit and a capacitive delay circuit that notifies of a potential repetitive-based attack by sending an activity-detected signal that can be used to initiate an appropriate countermeasure response. Additionally, or independently, a computing device incorporating repetitive SCA countermeasures can include at least one storage unit that can store an incoming input signal, at least one comparator to compare the incoming input signal with another signal and indicate a match, and a counter that increments upon the match. When the counter reaches a specified limit, a limit-exceeded signal can be sent to notify of a potential repetitive-based attack and initiate an appropriate countermeasure response.

Abstract: An apparatus includes a processing circuit and a storage device. The processing circuit is configured to perform one or more processing operations in response to one or more instructions to generate an anchored-data element. The storage device is configured to store the anchored-data element. A format of the anchored-data element includes an identification item, an overlap item, and a data item. The data item is configured to hold a data value of the anchored-data element. The identification item indicates an anchor value for the data value or one or more special values.

Abstract: Non-volatile storage circuitry is provided as primary storage accessible to processing circuitry, e.g. as registers, a cache, scratchpad memory, TLB or on-chip RAM. Power control circuitry powers down a given region of the non-volatile storage circuitry when information stored in said given region is not being used. This provides opportunities for more frequent power savings than would be possible if primary storage was implemented using volatile storage.

Abstract: A computing device can include a comparator coupled to an I/O pin of the computing device; a storage unit coupled to the comparator; and a counter coupled to receive an output of the comparator, an output of the counter being coupled to a computation engine to provide a limit-exceeded signal to the computation engine, wherein the counter comprises a volatile counter and a nonvolatile storage, wherein the nonvolatile storage stores a bit for each top volatile count number of events identified by the volatile counter. The computing device can further include a backup power source coupled to the volatile counter; and readout circuitry and control logic coupled to the volatile counter and to the nonvolatile storage, the readout circuitry and control logic being configured to control operations of the volatile counter during an error event and determine a total number of events. The computing device can be a smart card.

Abstract: Briefly, example methods, apparatuses, and/or articles of manufacture are disclosed that may be implemented, in whole or in part, using one or more computing devices to facilitate and/or support one or more operations and/or techniques for an autonomous pseudo-random seed generator (APRSG) for embedded computing devices, which may include IoT-type devices, such as implemented in connection with one or more computing and/or communication networks and/or protocols.

Abstract: Briefly, example methods, apparatuses, and/or articles of manufacture are disclosed that may be implemented, in whole or in part, using one or more computing devices to facilitate and/or support one or more operations and/or techniques for creating and/or enhancing hardware obscurity via one or more randomization points, such as implemented in connection with one or more computing and/or communication networks and/or protocols.

Abstract: Briefly, example methods, apparatuses, and/or articles of manufacture are disclosed that may be implemented, in whole or in part, using one or more computing devices to facilitate and/or support one or more operations and/or techniques for autonomous verification of circuit design for IoT-type devices, which may include, for example, IoT-type devices operating in resource constrained or like environments.

Abstract: An apparatus is provided to enable power supply input to be isolated from power supply output. Power is received from a first power signal at a first of a plurality of charge stores. A second power signal is output from a second of the plurality of charge stores. The second power signal is isolated from the first power supply. The first charge store can be charged from the power input whilst isolated from the power output. The second charge store can be discharged to the power output, while isolated from the power input.

Abstract: An apparatus is provided, that includes an instruction decoder responsive to an anchored-data processing instruction, to generate one or more control signals. Conversion circuitry is responsive to the one or more control signals to perform a conversion from a data value to an anchored-data select value. The conversion is based on anchor metadata indicative of a given range of significance for the anchored-data select value. Output circuitry is responsive to the one or more control signals, to write the anchored-data select value to a register.

Abstract: Processing circuitry may support processing of anchor-data values comprising one or more anchored-data elements which represent portions of bits of a two's complement number. The anchored-data processing may depend on anchor information indicating at least one property indicative of a numeric range representable by the result anchored-data element or the anchored-data value. When the operation causes an overflow or an underflow, usage information may be stored indicating a cause of the overflow or underflow and/or an indication of how to update the anchor information and/or number of elements in the anchored-data value to prevent the overflow or underflow. This can support dynamic range adjustment in software algorithms which involve anchored-data processing.

Abstract: An apparatus includes a power input, a power output, and a plurality of independent powering units each comprising at least one charge store. Each of the plurality of powering units is capable of receiving power from the power input while isolating the power output, and each of the plurality of powering units is capable of outputting power to the power output while isolating the power input.

Abstract: Non-volatile storage circuitry is provided as primary storage accessible to processing circuitry, e.g. as registers, a cache, scratchpad memory, TLB or on-chip RAM. Power control circuitry powers down a given region of the non-volatile storage circuitry when information stored in said given region is not being used. This provides opportunities for more frequent power savings than would be possible if primary storage was implemented using volatile storage.

Abstract: Processing circuitry may support processing of anchor-data values comprising one or more anchored-data elements which represent portions of bits of a two's complement number. The anchored-data processing may depend on anchor information indicating at least one property indicative of a numeric range representable by the result anchored-data element or the anchored-data value. When the operation causes an overflow or an underflow, usage information may be stored indicating a cause of the overflow or underflow and/or an indication of how to update the anchor information and/or number of elements in the anchored-data value to prevent the overflow or underflow. This can support dynamic range adjustment in software algorithms which involve anchored-data processing.

Abstract: An apparatus is provided, that includes an instruction decoder responsive to an anchored-data processing instruction, to generate one or more control signals. Conversion circuitry is responsive to the one or more control signals to perform a conversion from a data value to an anchored-data select value. The conversion is based on anchor metadata indicative of a given range of significance for the anchored-data select value. Output circuitry is responsive to the one or more control signals, to write the anchored-data select value to a register.

Abstract: Various implementations described herein are directed to providing time-dependent authentication of a sending device. A message to a designated receiver is prepared. A portion of at least one secret identifier value of the sending device is retrieved. A portion of time information is retrieved. An authentication field is produced using the portion of the at least one secret identifier value and the portion of the time information. The authentication field is attached to the message. The message is transmitted to the designated receiver.

Abstract: An apparatus and method are provided for processing input operand values. The apparatus has a set of vector data storage elements, each vector data storage element providing a plurality of sections for storing data values. A plurality of lanes are considered to be provided within the set of storage elements, where each lane comprises a corresponding section from each vector data storage element. Processing circuitry is arranged to perform an arithmetic operation on an input operand value comprising a plurality of portions, by performing an independent arithmetic operation on each of the plurality of portions, in order to produce a result value comprising a plurality of result portions. Storage circuitry is arranged to store the result value within a selected lane of the plurality of lanes, such that each result portion is stored in a different vector data storage element within the corresponding section for the selected lane.