Patents by Inventor Christopher Neal Hinds

Christopher Neal Hinds has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20200257499
    Abstract: Processing circuitry may support processing of anchor-data values comprising one or more anchored-data elements which represent portions of bits of a two's complement number. The anchored-data processing may depend on anchor information indicating at least one property indicative of a numeric range representable by the result anchored-data element or the anchored-data value. When the operation causes an overflow or an underflow, usage information may be stored indicating a cause of the overflow or underflow and/or an indication of how to update the anchor information and/or number of elements in the anchored-data value to prevent the overflow or underflow. This can support dynamic range adjustment in software algorithms which involve anchored-data processing.
    Type: Application
    Filed: February 6, 2019
    Publication date: August 13, 2020
    Inventors: David Raymond LUTZ, Neil BURGESS, Christopher Neal HINDS
  • Publication number: 20200249942
    Abstract: An apparatus is provided, that includes an instruction decoder responsive to an anchored-data processing instruction, to generate one or more control signals. Conversion circuitry is responsive to the one or more control signals to perform a conversion from a data value to an anchored-data select value. The conversion is based on anchor metadata indicative of a given range of significance for the anchored-data select value. Output circuitry is responsive to the one or more control signals, to write the anchored-data select value to a register.
    Type: Application
    Filed: May 29, 2019
    Publication date: August 6, 2020
    Inventors: David Raymond LUTZ, Neil BURGESS, Christopher Neal HINDS, Nigel John STEPHENS
  • Publication number: 20200153826
    Abstract: Various implementations described herein are directed to providing time-dependent authentication of a sending device. A message to a designated receiver is prepared. A portion of at least one secret identifier value of the sending device is retrieved. A portion of time information is retrieved. An authentication field is produced using the portion of the at least one secret identifier value and the portion of the time information. The authentication field is attached to the message. The message is transmitted to the designated receiver.
    Type: Application
    Filed: September 27, 2018
    Publication date: May 14, 2020
    Inventors: Christopher Neal Hinds, David Raymond Lutz
  • Patent number: 10579338
    Abstract: An apparatus and method are provided for processing input operand values. The apparatus has a set of vector data storage elements, each vector data storage element providing a plurality of sections for storing data values. A plurality of lanes are considered to be provided within the set of storage elements, where each lane comprises a corresponding section from each vector data storage element. Processing circuitry is arranged to perform an arithmetic operation on an input operand value comprising a plurality of portions, by performing an independent arithmetic operation on each of the plurality of portions, in order to produce a result value comprising a plurality of result portions. Storage circuitry is arranged to store the result value within a selected lane of the plurality of lanes, such that each result portion is stored in a different vector data storage element within the corresponding section for the selected lane.
    Type: Grant
    Filed: December 6, 2017
    Date of Patent: March 3, 2020
    Assignee: ARM Limited
    Inventors: Christopher Neal Hinds, Neil Burgess, David Raymond Lutz
  • Publication number: 20200012783
    Abstract: A computing device can include a comparator coupled to an I/O pin of the computing device; a storage unit coupled to the comparator; and a counter coupled to receive an output of the comparator, an output of the counter being coupled to a computation engine to provide a limit-exceeded signal to the computation engine, wherein the counter comprises a volatile counter and a nonvolatile storage, wherein the nonvolatile storage stores a bit for each top volatile count number of events identified by the volatile counter. The computing device can further include a backup power source coupled to the volatile counter; and readout circuitry and control logic coupled to the volatile counter and to the nonvolatile storage, the readout circuitry and control logic being configured to control operations of the volatile counter during an error event and determine a total number of events. The computing device can be a smart card.
    Type: Application
    Filed: May 10, 2019
    Publication date: January 9, 2020
    Inventors: Carl Wayne VINEYARD, Christopher Neal HINDS, Subbayya Chowdary YANAMADALA, Asaf SHEN
  • Publication number: 20200012822
    Abstract: A computing device incorporating repetitive side channel attack (SCA) countermeasures can include a timer circuit and a capacitive delay circuit that notifies of a potential repetitive-based attack by sending an activity-detected signal that can be used to initiate an appropriate countermeasure response. Additionally, or independently, a computing device incorporating repetitive SCA countermeasures can include at least one storage unit that can store an incoming input signal, at least one comparator to compare the incoming input signal with another signal and indicate a match, and a counter that increments upon the match. When the counter reaches a specified limit, a limit-exceeded signal can be sent to notify of a potential repetitive-based attack and initiate an appropriate countermeasure response.
    Type: Application
    Filed: July 9, 2018
    Publication date: January 9, 2020
    Inventors: Carl Wayne VINEYARD, Christopher Neal HINDS, Adeline-Fleur FLEMING
  • Patent number: 10459688
    Abstract: An apparatus comprises: processing circuitry to perform data processing; and an instruction decoder to control the processing circuitry to perform an anchored-data processing operation to generate an anchored-data element. The anchored-data element has an encoding including type information indicative of whether the anchored-data element represents: a portion of bits of a two's complement number, said portion of bits corresponding to a given range of significance representable using the anchored-data element; or a special value other than said portion of bits of a two's complement number.
    Type: Grant
    Filed: February 6, 2019
    Date of Patent: October 29, 2019
    Assignee: ARM Limited
    Inventors: Neil Burgess, Christopher Neal Hinds, David Raymond Lutz
  • Patent number: 10394524
    Abstract: Apparatus and corresponding methods are disclosed relating to circuitry to perform an arithmetic operation on one or more input operands, where the circuitry is responsive to an equivalence of a result value of the arithmetic operation with at least one of the one or more input operands, when the one or more input operands are not an identity element for the arithmetic operation, to generate a signal indicative of the equivalence. Idempotency (between at least one input operand and the result value) is thus identified.
    Type: Grant
    Filed: February 14, 2018
    Date of Patent: August 27, 2019
    Assignee: ARM Limited
    Inventors: Christopher Neal Hinds, David Raymond Lutz
  • Patent number: 10216479
    Abstract: An apparatus and method are provided for performing arithmetic operations to accumulate floating-point numbers. The apparatus comprises execution circuitry to perform arithmetic operations, and decoder circuitry to decode a sequence of instructions. A convert and accumulate instruction is provided, and the decoder circuitry is responsive to decoding the convert and accumulate instruction to generate one or more control signals to control the execution circuitry to convert at least one floating-point operand identified by the convert and accumulate instruction into a corresponding N-bit fixed-point operand having M fraction bits, where M is less than N and M is dependent on a format of the floating-point operand. The execution circuitry accumulates each corresponding N bit fixed-point operand and a P bit fixed-point operand identified by the convert and accumulate instruction in order to generate a P bit fixed-point result value, where P is greater than N and also has M fraction bits.
    Type: Grant
    Filed: December 6, 2016
    Date of Patent: February 26, 2019
    Assignee: ARM LIMITED
    Inventors: David Raymond Lutz, Neil Burgess, Christopher Neal Hinds, Andreas Due Engh-Halstvedt
  • Publication number: 20180336372
    Abstract: Power is received from a first power signal at a first of a plurality of charge stores. A second power signal is output from a second of the plurality of charge stores. The second power signal is isolated from the first power supply.
    Type: Application
    Filed: May 1, 2018
    Publication date: November 22, 2018
    Inventors: Adeline-Fleur FLEMING, Carl Wayne VINEYARD, George McNeil LATTIMORE, Christopher Neal HINDS, Robert John HARRISON, Mikael RIEN, Abdellah BAKHALI, Robert Christiaan SCHOUTEN, Jean-Charles BOLINHAS
  • Publication number: 20180337767
    Abstract: Power is received from a first power signal a first of a plurality of charge stores. A second power signal is output from a second of the plurality of charge stores. The second power signal is isolated from the first power supply.
    Type: Application
    Filed: May 22, 2017
    Publication date: November 22, 2018
    Inventors: Robert John HARRISON, Mikael RIEN, Carl Wayne VINEYARD, George McNeil LATTIMORE, Christopher Neal HINDS, Adeline-Fleur FLEMING
  • Publication number: 20180217815
    Abstract: An apparatus and method are provided for processing input operand values. The apparatus has a set of vector data storage elements, each vector data storage element providing a plurality of sections for storing data values. A plurality of lanes are considered to be provided within the set of storage elements, where each lane comprises a corresponding section from each vector data storage element. Processing circuitry is arranged to perform an arithmetic operation on an input operand value comprising a plurality of portions, by performing an independent arithmetic operation on each of the plurality of portions, in order to produce a result value comprising a plurality of result portions. Storage circuitry is arranged to store the result value within a selected lane of the plurality of lanes, such that each result portion is stored in a different vector data storage element within the corresponding section for the selected lane.
    Type: Application
    Filed: December 6, 2017
    Publication date: August 2, 2018
    Inventors: Christopher Neal HINDS, Neil BURGESS, David Raymond LUTZ
  • Publication number: 20180173498
    Abstract: Apparatus and corresponding methods are disclosed relating to circuitry to perform an arithmetic operation on one or more input operands, where the circuitry is responsive to an equivalence of a result value of the arithmetic operation with at least one of the one or more input operands, when the one or more input operands are not an identity element for the arithmetic operation, to generate a signal indicative of the equivalence. Idempotency (between at least one input operand and the result value) is thus identified.
    Type: Application
    Filed: February 14, 2018
    Publication date: June 21, 2018
    Inventors: Christopher Neal HINDS, David Raymond LUTZ
  • Publication number: 20180157464
    Abstract: An apparatus and method are provided for performing arithmetic operations to accumulate floating-point numbers. The apparatus comprises execution circuitry to perform arithmetic operations, and decoder circuitry to decode a sequence of instructions in order to generate control signals to control the arithmetic operations performed by the execution circuitry. A convert and accumulate instruction is provided, and the decoder circuitry is responsive to decoding such a convert and accumulate instruction within the sequence of instructions to generate one or more control signals to control the execution circuitry. In particular, the execution circuitry is responsive to such control signals to convert at least one floating-point operand identified by the convert and accumulate instruction into a corresponding N-bit fixed-point operand having M fraction bits, where M is less than N and M is dependent on a format of the floating-point operand.
    Type: Application
    Filed: December 6, 2016
    Publication date: June 7, 2018
    Inventors: David Raymond LUTZ, Neil BURGESS, Christopher Neal HINDS, Andreas Due ENGH-HALSTVEDT
  • Patent number: 9990179
    Abstract: Apparatus and a corresponding method are disclosed relating to circuitry to perform an arithmetic operation on one or more input operands, where the circuitry is responsive to an equivalence of a result value of the arithmetic operation with at least one of the one or more input operands, when the one or more input operands are not an identity element for the arithmetic operation, to generate a signal indicative of the equivalence. Idempotency (between at least one input operand and the result value) is thus identified.
    Type: Grant
    Filed: June 1, 2016
    Date of Patent: June 5, 2018
    Assignee: ARM Limited
    Inventors: Christopher Neal Hinds, David Raymond Lutz
  • Patent number: 9928031
    Abstract: Processing circuitry is provided to perform an overlap propagating operation on a first data value to generate a second data value, the first and second data values having a redundant representation representing a P-bit numeric value using an M-bit data value comprising a plurality of N-bit portions, where M>P>N. In the redundant representation, each N-bit portion other than a most significant N-bit portion includes a plurality of overlap bits having a same significance as a plurality of least significant bits of a following N-bit portion. Each N-bit portion of the second data value other than a least significant N-bit portion is generated by adding non-overlap bits of a corresponding N-bit portion of the first data value to the overlap bits of a preceding N-bit portion of the first data value. This provides a faster technique for reducing the chance of overflow during addition of the redundantly represented M-bit value.
    Type: Grant
    Filed: November 12, 2015
    Date of Patent: March 27, 2018
    Assignee: ARM LIMITED
    Inventors: Neil Burgess, David Raymond Lutz, Christopher Neal Hinds
  • Publication number: 20170351488
    Abstract: Apparatus and a corresponding method are disclosed relating to circuitry to perform an arithmetic operation on one or more input operands, where the circuitry is responsive to an equivalence of a result value of the arithmetic operation with at least one of the one or more input operands, when the one or more input operands are not an identity element for the arithmetic operation, to generate a signal indicative of the equivalence. Idempotency (between at least one input operand and the result value) is thus identified.
    Type: Application
    Filed: June 1, 2016
    Publication date: December 7, 2017
    Inventors: Christopher Neal HINDS, David Raymond LUTZ
  • Patent number: 9817661
    Abstract: A data processing system supports execution of program instructions having a rounding position input operand so as to generate control signals for controlling processing circuitry to process a floating point input operand with a significand value to generate an output result which depends upon a value from rounding the floating point input operand using a variable rounding point within the significand of the floating point input operand as specified by the rounding position input operand. In this way, processing operations having as inputs floating point operands and anchored number operands may be facilitated.
    Type: Grant
    Filed: October 7, 2015
    Date of Patent: November 14, 2017
    Assignee: ARM Limited
    Inventors: David Raymond Lutz, Christopher Neal Hinds, Neil Burgess
  • Patent number: 9778906
    Abstract: An apparatus comprises processing circuitry to perform a conversion operation to convert a floating-point value to a vector comprising a plurality of data elements representing respective bit significance portions of a binary value corresponding to the floating-point value.
    Type: Grant
    Filed: December 24, 2014
    Date of Patent: October 3, 2017
    Assignee: ARM Limited
    Inventors: David Raymond Lutz, Neil Burgess, Christopher Neal Hinds
  • Patent number: 9766857
    Abstract: An apparatus includes processing circuitry to perform one or more arithmetic operations for generating a result value based on at least one operand. For at least one arithmetic operation, the processing circuitry is responsive to programmable significance data indicative of a target significance for the result value, to generate the result value having the target significance. For example, this allows programmers to set a significance boundary for the arithmetic operation so that it is not necessary for the processing circuitry to calculate bit values having a significance outside the specified boundary, enabling a performance improvement.
    Type: Grant
    Filed: December 24, 2014
    Date of Patent: September 19, 2017
    Assignee: ARM Limited
    Inventors: David Raymond Lutz, Neil Burgess, Christopher Neal Hinds