Abstract: Transistor structures with source and drain contact metal structures comprising a lower portion of a first lateral dimension that is coupled with underlying channel material layers and an upper portion of a second lateral dimension that is coupled with an overlying via. The second lateral dimension is smaller than the first lateral dimension, enabling edge placement error associated with via patterning to be better accommodated. In some embodiments, an intervening dielectric liner is formed between an adjacent gate spacer dielectric material and the contact metal structures. The intervening dielectric liner may be formed, for example, by etching back a source or drain contact structure to form a self-aligned recess of a predetermined depth, forming a thin dielectric material layer upon sidewalls of the recess, and at least partially back filling a remainder of the recess with additional contact metal.