Abstract: A dose and focus monitor structure includes at least one complementary set of unit dose monitors and at least one complementary set of unit focus monitors. Each complementary set of unit dose monitors generate edges on a photoresist layer such that the edges move in opposite directions as a function of a dose offset. Each complementary set of unit focus monitors generates edges on the photoresist layer such that the edges move in opposite directions as a function of a focus offset. The dose and focus monitor structure generates self-compensating differential measurements of the dose offset and the focus offset such that the dose offset measurement and the focus offset measurement are independent of each other.

Abstract: Deformation of a substrate due to one or more processing steps is determined by measuring substrate alignment data at lithographic processing steps before and after the one or more processing steps. Any abnormal pattern in the alignment data differential is identified by comparing the calculated alignment data differential with previous data accumulated in a database. By comparing the abnormal pattern with previously identified tool-specific patterns for alignment data differential, a processing step that introduces the abnormal pattern and/or the nature of the abnormal processing can be identified, and appropriate process control measures can be taken to rectify any anomaly in the identified processing step.

Abstract: Cut spacer reference marks, targets having such cut spacer reference marks, and methods of making the same by forming spacer gratings around grating lines on a first layer, and fabricating a template mask that extends across and perpendicular to such spacer gratings. Cut spacer gratings are etched into a second layer using the template mask to superimpose at least a portion of the spacer gratings of the first layer into the second layer.

Abstract: A method for mask-to-wafer correlation among multiple masking levels of a semiconductor manufacturing process. The method includes creating compact targets containing structure patterns suitable for pattern placement, critical dimension and overlay measurement at a set of common locations on two or more patterning layers, and creating at least two masks containing functional circuit structure patterns and the compact targets at locations between functional circuit structure patterns. The method then includes measuring the targets, determining overlay variation between the masks, exposing and creating with one mask a first lithographic processing layer on a wafer, and exposing and creating with another mask a second lithographic processing layer on the wafer, over the first layer.

Abstract: A method of determining stitching errors in multiple lithographically exposed fields on a semiconductor layer during a semiconductor manufacturing process is provided. The method may include receiving a predetermined design distance corresponding to a plurality of petals associated with the multiple lithographically exposed fields and identifying a blossom within a single field-of-view (FOV) of a metrology tool, where the blossom is formed by a non-overlapping abutment of corners corresponding to the multiple lithographically exposed fields. The blossom may include the plurality of petals associated with the multiple lithographically exposed fields. Petal position errors may then be calculated based on both a coordinate position for each of the plurality of petals within the blossom and the predetermined design distance, whereby the calculated petal position errors are indicative of stitching errors for the multiple lithographically exposed fields.

Abstract: Cut spacer reference marks, targets having such cut spacer reference marks, and methods of making the same by forming spacer gratings around grating lines on a first layer, and fabricating an angled template mask that extends across and resides at an angle with respect to such spacer gratings. Angled, cut spacer gratings are etched into a second layer using the angled template mask to superimpose at least a portion of the spacer gratings of the first layer into the second layer.

Abstract: A method of determining stitching errors in multiple lithographically exposed fields on a semiconductor layer during a semiconductor manufacturing process is provided. The method may include receiving a predetermined design distance corresponding to a plurality of petals associated with the multiple lithographically exposed fields and identifying a blossom within a single field-of-view (FOV) of a metrology tool, where the blossom is formed by a non-overlapping abutment of corners corresponding to the multiple lithographically exposed fields. The blossom may include the plurality of petals associated with the multiple lithographically exposed fields. Petal position errors may then be calculated based on both a coordinate position for each of the plurality of petals within the blossom and the predetermined design distance, whereby the calculated petal position errors are indicative of stitching errors for the multiple lithographically exposed fields.

Abstract: A dose and focus monitor structure includes at least one complementary set of unit dose monitors and at least one complementary set of unit focus monitors. Each complementary set of unit dose monitors generate edges on a photoresist layer such that the edges move in opposite directions as a function of a dose offset. Each complementary set of unit focus monitors generates edges on the photoresist layer such that the edges move in opposite directions as a function of a focus offset. The dose and focus monitor structure generates self-compensating differential measurements of the dose offset and the focus offset such that the dose offset measurement and the focus offset measurement are independent of each other.

Abstract: Cut spacer reference marks, targets having such cut spacer reference marks, and methods of making the same by forming spacer gratings around grating lines on a first layer, and fabricating an angled template mask that extends across and resides at an angle with respect to such spacer gratings. Angled, cut spacer gratings are etched into a second layer using the angled template mask to superimpose at least a portion of the spacer gratings of the first layer into the second layer.

Abstract: Cut spacer reference marks, targets having such cut spacer reference marks, and methods of making the same by forming spacer gratings around grating lines on a first layer, and fabricating a template mask that extends across and perpendicular to such spacer gratings. Cut spacer gratings are etched into a second layer using the template mask to superimpose at least a portion of the spacer gratings of the first layer into the second layer.

Abstract: System, method and computer program product for configuring and controlling a facility to perform a manufacturing process and updating a tool controlling the process according to a model employed for mapping calculated coefficients that characterize non-linear variations observed of a product to actual control parameters governing the processes/tools used by the facility during the manufacturing process. The method enables real-time control of variation in an exposure step of a patterning process using an exposure tool to minimize a nonlinear variation in one or more pattern attributes by adjusting the exposure tool or the patterning process corresponding to the calculated coefficients. In the method, measurements of product attributes, obtained by finite sampling over a well defined domain, are projected onto a predefined reference mesh spanning the domain, using a physically based model comprised of functions constructed to be orthogonal and normalized over a discrete set of reference mesh locations.

Abstract: A wafer includes an active region and a kerf region surrounding at least a portion of the active region. The wafer also includes a target region having a rectangular shape with a width and length greater than the width, the target region including one or more target patterns, at least one of the target patterns being formed by two sub-patterns disposed at opposing corners of target rectangle disposable within the target region.

Abstract: System, method and computer program product for configuring and controlling a facility to perform a manufacturing process and updating a tool controlling the process according to a model employed for mapping calculated coefficients that characterize non-linear variations observed of a product to actual control parameters governing the processes/tools used by the facility during the manufacturing process. The method enables real-time control of variation in an exposure step of a patterning process using an exposure tool to minimize a nonlinear variation in one or more pattern attributes by adjusting the exposure tool or the patterning process corresponding to the calculated coefficients. In the method, measurements of product attributes, obtained by finite sampling over a well defined domain, are projected onto a predefined reference mesh spanning the domain, using a physically based model comprised of functions constructed to be orthogonal and normalized over a discrete set of reference mesh locations.

Abstract: An alignment feature disposed on a substrate, the alignment feature including a first lithographic pattern having a first aggregate geometric center point defined by a first sub-pattern comprising alignment marks having a first sub-pattern geometric center point arranged a distance (d0) in a first direction from the first aggregate geometric center point, and a second sub-pattern comprising alignment marks having a second sub-pattern geometric center point arranged the distance d0 in a reciprocal direction of the first direction from the first aggregate geometric center point.

Abstract: System, method and computer program product including instructions executed by a processor system for configuring and controlling a facility to perform a manufacturing process and updating a tool controlling the process according to a model employed for mapping calculated coefficients that characterize non-linear variations observed of a product to actual control parameters governing the processes/tools used by the facility during the manufacturing process. In a semiconductor manufacturing process, the method enables real-time control of variation in an exposure step of a patterning process using an exposure tool to minimize a nonlinear variation in one or more pattern attributes by adjusting the exposure tool or the patterning process corresponding to the calculated coefficients. In the method, measurements of product attributes, obtained by finite sampling over a well defined domain (e.g.

Abstract: An alignment feature disposed on a substrate, the alignment feature including a first lithographic pattern having a first aggregate geometric center point defined by a first sub-pattern comprising alignment marks having a first sub-pattern geometric center point arranged a distance (d0) in a first direction from the first aggregate geometric center point, and a second sub-pattern comprising alignment marks having a second sub-pattern geometric center point arranged the distance d0 in a reciprocal direction of the first direction from the first aggregate geometric center point.

Abstract: Deformation of a substrate due to one or more processing steps is determined by measuring substrate alignment data at lithographic processing steps before and after the one or more processing steps. Any abnormal pattern in the alignment data differential is identified by comparing the calculated alignment data differential with previous data accumulated in a database. By comparing the abnormal pattern with previously identified tool-specific patterns for alignment data differential, a processing step that introduces the abnormal pattern and/or the nature of the abnormal processing can be identified, and appropriate process control measures can be taken to rectify any anomaly in the identified processing step.

Abstract: A wafer includes an active region and a kerf region surrounding at least a portion of the active region. The wafer also includes a target region having a rectangular shape with a width and a length greater than the width, the target region including one or more target patterns, at least one of the target patterns being formed by two sub-patterns disposed at opposing corners of a target rectangle disposable within the target region.

Abstract: A target system for determining positioning error between lithographically produced integrated circuit fields on at least one lithographic level. The target system includes a first target pattern on a lithographic field containing an integrated circuit pattern, with the first target pattern comprising a plurality of sub-patterns symmetric about a first target pattern center and at a same first distance from the first target pattern center. The target system also includes a second target pattern on a different lithographic field, with the second target pattern comprising a plurality of sub-patterns symmetric about a second target pattern center and at a same second distance from the second target pattern center. The second target pattern center is intended to be at the same location as the first target pattern center. The centers of the first and second target patterns may be determined and compared to determine positioning error between the lithographic fields.

Abstract: System, method and computer program product including instructions executed by a processor system for configuring and controlling a facility to perform a manufacturing process and updating a tool controlling the process according to a model employed for mapping calculated coefficients that characterize non-linear variations observed of a product to actual control parameters governing the processes/tools used by the facility during the manufacturing process. In a semiconductor manufacturing process, the method enables real-time control of variation in an exposure step of a patterning process using an exposure tool to minimize a nonlinear variation in one or more pattern attributes by adjusting the exposure tool or the patterning process corresponding to the calculated coefficients. In the method, measurements of product attributes, obtained by finite sampling over a well defined domain (e.g.