Abstract: A method for ensuring that a memory array such as a ferroelectric memory array is properly electrically connected. The method may be performed, for example, prior to a read or write cycle, during functional testing of the memory array, etc. In one implementation, the memory array is read and the data set including a data bit from each cell is stored in a register. A solid logic 0's pattern is written into the memory array, and each cell is read. If no cell returns a logic 1, it is determined that the memory array is properly connected and the register data values are written to the memory array. If one or more cells returns a logic 1, it is determined that the memory array is improperly connected, the register data values are written to the memory array, and the memory array is removed and reinstalled.

Abstract: A computer-implemented method for writing to a printed memory device is disclosed. The computer-implemented method includes determining, by a microcontroller, a first encoding scheme from among a plurality of encoding schemes to write a first data portion from among a plurality of data portions, wherein the first encoding scheme comprises a first voltage and a first pulse width to be used to write the first data portion; providing, by the microcontroller, the first encoding scheme to an application-specific integrated circuit (ASIC); selecting, by the ASIC, a first target memory cell of the printed memory device corresponding to a first word line and a first bit line for the first data portion to be written; and writing, by the ASIC, the first data portion to the first target memory cell using the first encoding scheme.

Abstract: A computer-implemented method for testing a printed memory device is provided. The computer-implemented method includes performing, by a controller, a first read operation on a cell of the printed memory device; performing, by the controller, a second read operation on the cell; converting, by the controller, a first result of the first read operation and a second results of the second read operation to a first digital value and a second digital value, respectively; comparing, by the controller, the first digital value and the second digital value to a first predetermined threshold and a second predetermined threshold, respectively, wherein the first predetermined threshold is a low threshold and the second predetermined threshold is a high threshold; and providing, by the controller, a result of the test for the printed memory device based on the comparing.

Abstract: A computer-implemented method for writing to a printed memory device is disclosed. The computer-implemented method includes determining, by a microcontroller, a first encoding scheme from among a plurality of encoding schemes to write a first data portion from among a plurality of data portions, wherein the first encoding scheme comprises a first voltage and a first pulse width to be used to write the first data portion; providing, by the microcontroller, the first encoding scheme to an application-specific integrated circuit (ASIC); selecting, by the ASIC, a first target memory cell of the printed memory device corresponding to a first word line and a first bit line for the first data portion to be written; and writing, by the ASIC, the first data portion to the first target memory cell using the first encoding scheme.

Abstract: A computer-implemented method for writing to and reading from a printed memory device is provided. Data to be written to the printed memory device is segmented into a plurality of data portions. Each data portion of the plurality of data portions is written to a memory cell of the printed memory as a tuple using a determined encoding scheme that is characterized by a voltage and a pulse width. The voltage that is used for the encoding scheme is within a predetermined polarization regime of the printed memory device. Tuples of data can be read from memory cells of the printed memory using a decoding scheme.

Abstract: A computer-implemented method for testing a printed memory device is provided. The computer-implemented method includes performing, by a controller, a first read operation on a cell of the printed memory device; performing, by the controller, a second read operation on the cell; converting, by the controller, a first result of the first read operation and a second results of the second read operation to a first digital value and a second digital value, respectively; comparing, by the controller, the first digital value and the second digital value to a first predetermined threshold and a second predetermined threshold, respectively, wherein the first predetermined threshold is a low threshold and the second predetermined threshold is a high threshold; and providing, by the controller, a result of the test for the printed memory device based on the comparing.

Abstract: A radio frequency identification (RFID) technique is disclosed. The technique includes a printed RFID antenna array including at least three printed RFID antenna elements and an RFID reader device with at least one RFID reader antenna sized to transmit excitation energy to a number N>1 of printed RFID antenna elements of the printed RFID antenna array, where N is less than a total number of printed RFID antenna elements of the printed RFID antenna array. The RFID reader antenna is configured to receive a plurality of compound signals from respective subarrays consisting of N of the printed RFID antenna elements of the printed RFID antenna array. The RFID reader device also includes a demodulator, a decoder, and an output interface.

Abstract: A method for ensuring that a memory array such as a ferroelectric memory array is properly electrically connected. The method may be performed, for example, prior to a read or write cycle, during functional testing of the memory array, etc. In one implementation, the memory array is read and the data set including a data bit from each cell is stored in a register. A solid logic 0's pattern is written into the memory array, and each cell is read. If no cell returns a logic 1, it is determined that the memory array is properly connected and the register data values are written to the memory array. If one or more cells returns a logic 1, it is determined that the memory array is improperly connected, the register data values are written to the memory array, and the memory array is removed and reinstalled.

Abstract: A component subsystem and a method for authenticating the component subsystem. The component subsystem may be installed in a host device. The method can include an authentication protocol, wherein the host device sends a test voltage value to the component subsystem which, in turn, generates a test voltage based on the test voltage value. The test voltage is applied to a test cell that includes a wordline, a bitline, and a memory film. A response voltage is read from the bitline and compared to an expected value. If the response voltage matches the expected value, host device and/or component subsystem functionality is enabled. If the response voltage does not match the expected value, the host device and/or component subsystem functionality is disabled.

Abstract: A component subsystem and a method for authenticating the component subsystem. The component subsystem may be installed in a host device. The method can include an authentication protocol, wherein the host device sends a test voltage value to the component subsystem which, in turn, generates a test voltage based on the test voltage value. The test voltage is applied to a test cell that includes a wordline, a bitline, and a memory film. A response voltage is read from the bitline and compared to an expected value. If the response voltage matches the expected value, host device and/or component subsystem functionality is enabled. If the response voltage does not match the expected value, the host device and/or component subsystem functionality is disabled.

Abstract: Systems include a transceiver having a transceiver antenna, a transponder positioned a first distance from the transceiver, and an intermediate structure positioned a second distance from the transponder (where the first distance is greater than the second distance). The transponder has a transponder antenna, and the intermediate structure has an intermediate antenna (and a capacitor). The transponder antenna is a first size antenna (smallest), the intermediate antenna is a second size antenna (bigger), and the transceiver antenna is a third size antenna (biggest). The intermediate structure provides field lines between the transceiver antenna and the transponder antenna that the transponder antenna is otherwise incapable of fully receiving from the transceiver antenna. This causes the intermediate antenna to transfer voltage received from the transceiver antenna to the transponder antenna.

Abstract: A component subsystem and a method for authenticating the component subsystem. The component subsystem may be installed in a host device. The method can include an authentication protocol, wherein the host device sends a test voltage value to the component subsystem which, in turn, generates a test voltage based on the test voltage value. The test voltage is applied to a test cell that includes a wordline, a bitline, and a memory film. A response voltage is read from the bitline and compared to an expected value. If the response voltage matches the expected value, host device and/or component subsystem functionality is enabled. If the response voltage does not match the expected value, the host device and/or component subsystem functionality is disabled.