Abstract: A semiconductor device with a current terminal region located in a device active area of a substrate of the device. A guard region is located in a termination area of the device. A plurality of floating field plates are located in the termination area and are ohmically coupled to the guard region. The floating field plates and guard region act in some embodiments to “smooth” the electrical field distribution along the termination area.

Abstract: A semiconductor device with a current terminal region located in a device active area of a substrate of the device. A guard region is located in a termination area of the device. A plurality of floating field plates are located in the termination area and are ohmically coupled to the guard region. The floating field plates and guard region act in some embodiments to “smooth” the electrical field distribution along the termination area.

Abstract: An RF power transistor with a metal design (70) comprises a drain pad (72) and a plurality of metal drain fingers (74) extending from the drain pad, wherein at least one metal drain finger comprises one or more sections of metal (74-1, 74-2, 100-1, 100-2, 100-3), each section of metal including of one or more branch (54-1, 54-2, 116-1, 116-2, 116-11, 116-21, 116-41) of metal having a metal width maintained within a bamboo regime.

Abstract: An RF power transistor with a metal design (70) comprises a drain pad (72) and a plurality of metal drain fingers (74) extending from the drain pad, wherein at least one metal drain finger comprises one or more sections of metal (74-1, 74-2, 100-1, 100-2, 100-3), each section of metal including of one or more branch (54-1, 54-2, 116-1, 116-2, 116-11, 116-21, 116-41) of metal having a metal width maintained within a bamboo regime.

Abstract: A semiconductor device (10) having a gate (15), a source (19), and a drain (20) with a gate bus (25) and first ground shield (24) patterned from a first metal layer and a second ground shield (31) patterned from a second metal layer. The first ground shield (24) and the second ground shield (31) lower the capacitance of device (10) making it suitable for high frequency applications and housing in a plastic package.

Abstract: A semiconductor device (10) having a gate (15), a source (19), and a drain (20) with a gate bus (25) and first ground shield (24) patterned from a first metal layer and a second ground shield (31) patterned from a second metal layer. The first ground shield (24) and the second ground shield (31) lower the capacitance of device (10) making it suitable for high frequency applications and housing in a plastic package.

Abstract: A semiconductor component includes a substrate (101), an electrode (105) located over the substrate (101), a heavily doped region (542) located in the substrate (101) and self-aligned to the electrode (105), an other heavily doped region (543) located in the substrate (101), a lightly doped region (422) located in the substrate (101) between the heavily doped regions (542, 543) and self-aligned to the electrode (105), and another lightly doped region (432) located in the substrate (101) between the lightly doped region (422) and the other heavily doped region (543).

Abstract: A high frequency power FET device (22) is integrated with passive components (23,24,26,28,31), an electro-static discharge (ESD) device (27,127,227), and/or a logic structure (29) on a semiconductor body (13) to form a monolithic high frequency integrated circuit structure (10). The high frequency power FET device (22) includes a grounded source configuration. The logic structure (29) utilizes the high frequency power FET structure in a grounded source configuration as one device in a CMOS implementation.

Abstract: A junction isolated P-well is formed for high performance BiCMOS. Two dopants of opposite conductivity types are implanted and co-diffused inside an annular N-type region to form a narrow N-type buried layer positioned between two P-type regions. N-type buried layer is formed having P-type doped regions above and below the N-type buried layer so that the N-type buried layer is narrow. The P-type region above the N-type buried layer provides for a retrograde profile of the P-well formed above it. Besides the P-well isolation, the P-type region below the N-type buried layer acts as a ground plane which collects noise, which helps to prevent it from being coupled to other devices of the BiCMOS circuit.

Abstract: A junction isolated P-well is formed for high performance BiCMOS. Two dopants of opposite conductivity types are implanted and co-diffused inside an annular N-type region to form a narrow N-type buried layer positioned between two P-type regions. N-type buried layer is formed having P-type doped regions above and below the N-type buried layer so that the N-type buried layer is narrow. The P-type region above the N-type buried layer provides for a retrograde profile of the P-well formed above it. Besides the P-well isolation, the P-type region below the N-type buried layer acts as a ground plane which collects noise, which helps to prevent it from being coupled to other devices of the BiCMOS circuit.