Abstract: An improved memory module and its use in a computer system is provided. The module includes a DSP first and second individually addressable banks of memory chips. The first bank is configured to function principally under the control of the signal processing element and the second bank is configured to function principally under the control of a system memory controller, although all the portions of each of the memory banks is addressable by both the signal processing element and the system memory controller. Both banks of memory chips can be placed in at least one higher power state and at least one lower power state by either the system memory controller or the DSP. The activity of each bank is sensed while in the higher power state, and the condition of each of the banks is sensed with respect to any activity during operation of the memory bank at the higher power state.

Abstract: This invention provides a method of providing contraception which comprises administering to a female of child bearing age a combination of a non-uterotrophic anti-estrogen and a progestin for 28 days per 28-day menstrual cycle.

Abstract: A fluorescent strip window envelope for use with PC postage printed inserts. The envelope has a front wall and a rear wall, a top edge, a bottom edge, a right edge and a left edge. The envelope has a postage indicia window formed in the front wall in an upper right hand region thereof. The envelope is sized to accommodate at least three tri-folded sheets of standard sized letter paper sheets or a standard business courtesy envelope as inserts such that when the insert is inserted into the envelope there is less than about a 5% skew of the insert relative to the envelope and to expose the postage indicia printed on the insert. The envelope is free of FIM marks, and in lieu thereof has fluorescent strips printed on the right side top edge and the upper right side edge of the envelope.

Abstract: A semiconductor circuit for providing decoupling capacitance to an integrated circuit voltage supply that includes a decoupling capacitance comprised of an array of memory cells connected in series at a node and a source of biasing voltage connected to the array of memory cells at the node for maintaining the voltage level at the node lower than the voltage level of the voltage supply.

Abstract: A semiconductor circuit for providing decoupling capacitance to an integrated circuit voltage supply that includes a decoupling capacitance comprised of an array of memory cells connected in series at a node and a source of biasing voltage connected to the array of memory cells at the node for maintaining the voltage level at the node lower than the voltage level of the voltage supply.

Abstract: An electronic semiconductor module, either memory or logic, having a driver circuit which includes a multiplicity of driver transistors, together with circuitry for simultaneously applying a first positive bias to a first select number of driver transistors to activate them to an operational state, a second positive bias to a second select number of driver transistors to place them in readiness for activation, and a negative bias to the remaining driver transistors to place them in a fully inactive state thereby reducing noise in the driver circuit. The first positive bias is greater than the transistor threshold voltage, preferably greater than two volts, the second positive bias is less than the threshold voltage, preferably less than one volt, and the negative bias is in the order of minus 0.3 volt.

Abstract: This invention provides 5&agr;-pregnane-3,&bgr;,(20S), 21-triol, 20-O-&bgr;-glucuronide and 5&agr;-pregnane-3&bgr;,20R-diol, 20-O-&bgr;-glucuronide and pharmaceutically acceptable salts thereof which are useful as progestational agents.

Abstract: A delay line, in accordance with the invention, includes a plurality of delay elements connecting an input and an output, the delay elements for causing a delay to be introduced to a signal passing through the delay elements. A voltage device is included for regulating power to the plurality of delay elements, the voltage device being adjustable to provide at least one predetermined voltage to the delay elements such that the delay in the delay elements is modified according to the predetermined voltage(s). The delay line may be employed in a delay locked loop, a clock circuit or other circuits.

Abstract: The invention features a novel recombinant polypeptide that transactivates the somatostatin promoter, the polypeptide being present in pancreatic duct cells and not present in pancreatic &agr;-cells, the polypeptide being encoded by a gene which encodes a protein on the order of 31 kd.

Abstract: A semiconductor circuit for providing decoupling capacitance to an integrated circuit voltage supply that includes a decoupling capacitance comprised of an array of memory cells connected in series at a node and a source of biasing voltage connected to the array of memory cells at the node for maintaining the voltage level at the node lower than the voltage level of the voltage supply.

Abstract: A method and structure for decoding n input signals and their complements to one of m output signals is provided. A capacitive network is provided having m output nodes. The output nodes are precharged to a given voltage value. N input signals and their complements are provided each having either a high value or a low value. At least one but less than all of the output nodes are discharged to a value less than the given voltage but greater than ground in output patterns responsive to given input patterns of the true and complement values of the input signals. The output patterns of the discharged nodes is such as to provide one and only one discharged or one and only one undischarged node for any given pattern of input signals. Preferably the capacitive network includes NMOS inversion capacitors.

Abstract: OCD circuitry is provided for an integrated circuit having a split rail power supply providing a first and a second voltage. The OCD circuitry comprises a tristate logic circuit adapted to control the OCD and a detection circuit coupled to the tristate logic circuit and adapted to generate an inactivation signal that inactivates the OCD if the first voltage is low. The detection circuit preferably comprises a comparator that compares the first voltage to the second voltage, and that generates the inactivation signal if the first voltage is less than the second voltage. To prevent the inadvertent inactivation of the OCD circuitry, the detection circuit preferably is provided with a filter that sets a minimum time period that the first voltage must be low before the detection circuit generates the inactivation signal and thus inactivates the OCD circuitry.

Abstract: A nondestructive read, three device BICMOS gain cell for a DRAM memory having two FETs and one bipolar device. The gain cell has an improved access time (less latency), can operate for longer periods of time before a refresh operation is required, requires a smaller storage capacitance than a traditional DRAM cell, and can be produced commercially at lower costs than are presently available. In a preferred embodiment, the gain cell comprises an n channel metal oxide semiconductor field effect write transistor having its gate connected to a write word line WLw. Its drain is connected to a storage node Vs having a storage capacitance Cs associated therewith, and its source is connected to a write bit line BLw. An n channel metal oxide semiconductor field effect read transistor has its gate connected to the storage node Vs and its source connected to a read word line WLr. A PNP transistor has its base connected to the drain of the read transistor and its emitter connected to a read bit line BLr.

Abstract: The invention features a novel recombinant polypeptide that transactivates the somatostatin promoter, the polypeptide being present in pancreatic duct cells and not present in pancreatic .alpha.-cells, the polypeptide being encoded by a gene which encodes a protein on the order of 31 kd.

Abstract: A method and apparatus for using multi-level signals in a gain cell is shown. The method involves of first, storing a value of a multi-level signal in the gain cell. A stepping waveform is then applied to the gain cell and the gain cell outputs a conduction signal when the level of the stepping waveform corresponds to the value of the multilevel signal that is stored within the gain cell. Finally, the value of the multi-level signal is determined through the conduction signal and the corresponding level of the stepping waveform. The gain cell includes an input device, a storage device and a level comparator, which responds to the stepping waveform generated from a stepping signal generator and outputs the conduction signal for determining the value of the multi-level signal stored in the storage device.

Abstract: A gain cell in a memory array having read and write bitlines and wordlines, wherein the gain cell comprises a write transistor, a storage node, a read transistor, and a diode is disclosed. The write transistor allows the value of the write bitline to be stored onto the storage node when activated by the write wordline. The read transistor, which allows the stored value to be read, is coupled to the storage node and to the read bitline via the diode. The diode prevents the conduction of the read transistor in the opposite direction, thus preventing read interference from other cells and reducing bitline capacitance.

Abstract: A latch circuit includes a plurality of transistors, a set input for receiving a set signal coupled to a first transistor of the plurality of transistors, a reset input for receiving a reset signal coupled to a second transistor of the plurality of transistors, a third transistor of the plurality of transistors coupled to the first transistor and a fourth transistor of the plurality of transistors coupled to the first transistor, a fifth transistor of the plurality of transistors coupled to the second transistor, a sixth transistor of the plurality of transistors coupled to the second transistor, and a node coupled to an output device, the fourth transistor and the sixth transistor. A first feedback loop includes an inverter, the output device, the node and the fourth transistor. A second feedback loop includes the inverter, the output device, the node and the sixth transistor. The first feedback loop continuously outputs a first signal and the second feedback loop continuously outputs a second signal.

Abstract: A high performance receiver/decoder circuit combines input signal detection and decoding to a one-of-n selection signal in a single stage. Particularly when implemented in dynamic logic, speed of decoding is substantially increased while reset and precharge circuits and procedures are greatly simplified which is accomplished by placing logic trees in series with a latch circuit and a common connection to a transistor or other circuit for enabling input evaluation. The decoder is preferably implemented with a plurality of identical circuits with true and complement inputs selectively distributed thereto, as may be convenient to the circuit design.

Abstract: A dynamic bus system with a central precharge device is disclosed that utilizes a controller circuit with a one-shot generator and write synchronizing circuits in combination with logic output modules having pull-up/down devices. The issuance of the output enable (OE) signals is interlocked with the turn-off of the precharge. Thus, data is written to the dynamic bus only when the precharge device is inactive, avoiding bus collisions. The resulting circuitry not only ensures the precharging of the bus before the data write to the bus, but will allow the synchronized OE signals to be issued during the same clock phase as the precharge signal.

Abstract: A latch circuit includes a plurality of transistors, a set input for receiving a set signal coupled to a first transistor of the plurality of transistors, a reset input for receiving a reset signal coupled to a second transistor of the plurality of transistors, a third transistor of the plurality of transistors coupled to the first transistor and a fourth transistor of the plurality of transistors coupled to the first transistor, a fifth transistor of the plurality of transistors coupled to the second transistor, a sixth transistor of the plurality of transistors coupled to the second transistor, and a node coupled to an output device, the fourth transistor and the sixth transistor. A first feedback loop includes an inverter, the output device, the node and the fourth transistor. A second feedback loop includes the inverter, the output device, the node and the sixth transistor. The first feedback loop continuously outputs a first signal and the second feedback loop continuously outputs a second signal.