Abstract: Systems, apparatuses and methods may provide for determining a status of an enable signal and selecting a leaker resistance from a plurality of leaker resistances based at least in part on the status of the enable signal. Additionally, the selected leaker resistance may be applied to a data strobe line of a memory bus. In one example, the selected leaker resistance reduces ringback noise on the data strobe line.

Abstract: In an embodiment, a memory device may contain device processing logic and a mode register. The mode register may a register that may specify a mode of operation of the memory device. A field in the mode register may hold a value that may indicate whether a command associated with the memory device is disabled. The value may be held in the field until either the memory device is power-cycled or reset. The device processing logic may acquire an instance of the command. The device processing logic may determine whether the command is disabled based on the value held by the mode register. The device processing logic may not execute the instance of the command if the device processing logic determines the command is disabled. If the device processing logic determines the command is not disabled, the device processing logic may execute the instance of the command.

Abstract: A memory subsystem empirically tests performance parameters of I/O with a memory device. Based on the empirical testing, the memory subsystem can set the performance parameters specific to the system in which the memory subsystem is included. A test system performs the testing. For each of multiple different settings for multiple different I/O circuit parameters, the test system sets a value for each I/O circuit parameter, generates test traffic to stress test the memory device with the parameter value(s), and measures an operating margin for the I/O performance characteristic. The test system further executes a search function to determine values for each I/O circuit parameter at which the operating margin meets a minimum threshold and performance of at least one of the I/O circuit parameters is increased. The memory subsystem sets runtime values for the I/O circuit parameters based on the search function.

Abstract: Power gating control architectures. A memory device having at least a memory array and input/output (I/O) lines terminated on the memory device with termination circuitry coupled to receive a termination supply voltage (Vtt) with power gating circuitry to selectively gate the termination supply voltage in response to a power gating control signal (VttControl) is coupled with a processing core coupled with the memory device, the processing core to selectively assert and deassert the VttControl signal.

Abstract: In one embodiment, a system on a chip (SoC) includes a plurality of processor cores and a memory controller to control communication between the SoC and a memory coupled to the memory controller. The memory controller may be configured to send mirrored command and address signals to a first type of memory device and to send non-mirrored control and address signals to a second type of memory device. Other embodiments are described and claimed.

Abstract: Described herein is an apparatus for dynamically adjusting a voltage reference level for optimizing an I/O system to achieve a certain performance metric. The apparatus comprises: a voltage reference generator to generate a voltage reference; and a dynamic voltage reference control unit, coupled with the voltage reference generator, to dynamically adjust a level of the voltage reference in response to an event. The apparatus is used to perform the method comprising: generating a voltage reference for an input/output (I/O) system; determining a worst case voltage level of the voltage reference; dynamically adjusting, via a dynamic voltage reference control unit, the voltage reference level based on determining the worst case voltage level; and computing a center of an asymmetrical eye based on the dynamically adjusted voltage reference level.

Abstract: A memory controller issues a targeted refresh command. A specific row of a memory device can be the target of repeated accesses. When the row is accessed repeatedly within a time threshold (also referred to as “hammered” or a “row hammer event”), physically adjacent row (a “victim” row) may experience data corruption. The memory controller receives an indication of a row hammer event, identifies the row associated with the row hammer event, and sends one or more commands to the memory device to cause the memory device to perform a targeted refresh that will refresh the victim row.

Abstract: An I/O interface supports scrambling, where the scrambling can include nonlinear scrambling of the scrambling code, or dynamic bus inversion of the scrambling code, or selective switching of selected bits of the scrambling code, or a combination of these. The transmitting device includes a scrambler and the receiving device includes a descrambler. Both the scrambler and the descrambler generate a linear feedback scrambling code modified by applying one or more of the techniques mentioned above. The modified scrambling code may cause fewer than half of the scrambled output bits to be toggled with respect to a previous scrambled output. The scrambler applies the modified scrambling code to a signal to transmit. The descrambler applies the modified scrambling code to a received signal.

Abstract: In an embodiment, a memory device may contain device processing logic and a mode register. The mode register may a register that may specify a mode of operation of the memory device. A field in the mode register may hold a value that may indicate whether a command associated with the memory device is disabled. The value may be held in the field until either the memory device is power-cycled or reset. The device processing logic may acquire an instance of the command. The device processing logic may determine whether the command is disabled based on the value held by the mode register. The device processing logic may not execute the instance of the command if the device processing logic determines the command is disabled. If the device processing logic determines the command is not disabled, the device processing logic may execute the instance of the command.

Abstract: A transmission line interface circuit includes a voltage regulator to control a voltage swing of the transmission line interface circuit for signal transmission. The transmission line interface circuit includes complementary driver elements, including a p-type driver element to pull up the transmission line in response to a logic high, and an n-type driver element to pull down the transmission line in response to a logic low. The voltage regulator is coupled between one of the driver elements and a respective voltage reference to reduce a voltage swing of the transmission line interface circuit.

Abstract: Described herein is an apparatus for dynamically adjusting a voltage reference level for optimizing an I/O system to achieve a certain performance metric. The apparatus comprises: a voltage reference generator to generate a voltage reference; and a dynamic voltage reference control unit, coupled with the voltage reference generator, to dynamically adjust a level of the voltage reference in response to an event. The apparatus is used to perform the method comprising: generating a voltage reference for an input/output (I/O) system; determining a worst case voltage level of the voltage reference; dynamically adjusting, via a dynamic voltage reference control unit, the voltage reference level based on determining the worst case voltage level; and computing a center of an asymmetrical eye based on the dynamically adjusted voltage reference level.

Abstract: Dynamic bus inversion (DBI) for programmable levels of a ratio of ones and zeros. A transmitting device identifies a number and/or ratio of ones and zeros in a noninverted version of a signal to be transmitted (“noninverted signal”) and a number and/or ratio of ones and zeros in an inverted version of the signal (“inverted signal”). The transmitting device can calculate whether a difference of ones and zeros in the noninverted signal or a difference of ones and zeros in the inverted signal provides a calculated average ratio of ones to zeros closer to a target ratio. The transmitting device sends the signal that achieves provides the calculated average ratio closer to the target ratio.

Abstract: A memory device interface with a programmable driver. The memory device is associated with a memory controller, with one or more input/output (I/O) signal lines coupled between the memory device and the memory controller. The memory device includes an I/O signal line interface including a driver for each I/O signal line. The driver is a programmable driver to dynamically adjust an output voltage swing for transmission via the I/O signal line interface.

Abstract: Power gating circuits. A transistor stack is coupled between a voltage supply to provide a gated supply voltage. The supply voltage is greater than the maximum junction voltage of the individual transistors in the transistor stack. Termination circuitry for input/output (I/O) lines coupled to operate using the gated supply voltage. The termination circuitry comprising at least a resistive element coupled between an I/O interface and a termination voltage supply.

Abstract: Described herein is an apparatus for dynamically adjusting a voltage reference level for optimizing an I/O system to achieve a certain performance metric. The apparatus comprises: a voltage reference generator to generate a voltage reference; and a dynamic voltage reference control unit, coupled with the voltage reference generator, to dynamically adjust a level of the voltage reference in response to an event. The apparatus is used to perform the method comprising: generating a voltage reference for an input/output (I/O) system; determining a worst case voltage level of the voltage reference; dynamically adjusting, via a dynamic voltage reference control unit, the voltage reference level based on determining the worst case voltage level; and computing a center of an asymmetrical eye based on the dynamically adjusted voltage reference level.

Abstract: A memory controller issues a targeted refresh command. A specific row of a memory device can be the target of repeated accesses. When the row is accessed repeatedly within a time threshold (also referred to as “hammered” or a “row hammer event”), physically adjacent row (a “victim” row) may experience data corruption. The memory controller receives an indication of a row hammer event, identifies the row associated with the row hammer event, and sends one or more commands to the memory device to cause the memory device to perform a targeted refresh that will refresh the victim row.

Abstract: I/O parameters are adjusted based on a number of errors detected in a received training signal. A controller device sends the training signal while a memory device is in a training mode. The memory device samples the training signal and the system causes an adjustment to at least one I/O parameter based on a detected number of errors. Either the controller or the memory device can perform the error detection, depending on the configuration of the system. Either an I/O parameter of the controller or an I/O parameter of the memory device can be adjusted, depending on the configuration of the system.

Abstract: In an embodiment, a memory device may contain device processing logic and a mode register. The mode register may a register that may specify a mode of operation of the memory device. A field in the mode register may hold a value that may indicate whether a command associated with the memory device is disabled. The value may be held in the field until either the memory device is power-cycled or reset. The device processing logic may acquire an instance of the command. The device processing logic may determine whether the command is disabled based on the value held by the mode register. The device processing logic may not execute the instance of the command if the device processing logic determines the command is disabled. If the device processing logic determines the command is not disabled, the device processing logic may execute the instance of the command.

Abstract: A memory subsystem can test a memory device in situ, testing the performance of parameters of operation the device in the system it is built into during production. Thus, the system can detect the specific values that will work for one or more operating parameters for the memory device in actual runtime. A test component embedded in the memory subsystem can perform a stress test and identify specific bits or lines of memory that experience failure under one or more stresses. The system can then map out the failed bits or lines to prevent the bits/lines from being used in runtime of the system.

Abstract: In one example a controller comprises logic, at least partially including hardware logic, configured to implement a first iteration of an interference test on a communication interconnect comprising a victim lane and a first aggressor lane by generating a first set of pseudo-random patterns on the victim lane and the aggressor lane using a first seed and implement a second iteration of an interference test by advancing the seed on the first aggressor lane. Other examples may be described.