Abstract: A locking circuit for controlling access to locked segments of a shared memory includes a content-addressable memory for storing addresses of the locked memory segments and for simultaneously comparing a target address with the addresses of the locked memory segments and providing a match signal when the target address matches one of the addresses of the locked memory segments. During a memory access cycle, a target address is supplied to the content-addressable memory, and a control circuit is responsive to the match signal to inhibit completion of the memory access cycle. A locking ID, which identifies the processor or process that locked the memory segment, is stored in a second memory. During a memory access cycle, a requesting ID is compared with the locking ID of the locked segment which produced the match signal. When the locking ID and the requesting ID match, the memory access cycle is enabled.

Abstract: A content-addressable memory (CAM) consisting of an array of memory cells arranged in a matrix by rows and columns is disclosed in which each memory cell includes a pair of cross-coupled CMOS inverters for storing a representation of a single bit. The bits in each row of memory cells constitute a keyword. Keywords are entered into the memory one row at a time. All of the stored keywords are compared to a single search word simultaneously during a match operation. The CAM is prepared for a match operation by placing a charge on a match line associated with each row. If all the bits of the search word match the bits of the stored keyword, the associated match line remains charged producing a match signal for the row of memory cells. If any bit of the search word does not match the corresponding bit of the stored keyword, the associated match line is discharged producing a no-match signal for the row of memory cells.