Abstract: A digital phase detector circuit has an up/down counter for counting clock pulses (CPS) to determine the number of clock pulses that occur in the time interval between opposite edges of a first signal (VSC) and one edge of a reference signal (PL) synchronized with the clock pulses (CPS). A latch provides a first digital output signal (DES) which represents the number. The phase detector also has an analogue phase detector circuit having a flip-flop for producing a second signal (VCS') which corresponds to the first signal (VCS) and is synchronized with the clock pulses (CPS). Logic gates and determine the time intervals between corresponding edges of the first and second signals (VCS,VCS'), and a circuit element determines a phase error voltage (VS) from these time intervals. The voltage (VS) is digitized to provide a second digital output signal (AES).

Abstract: A digital oscillator produces a succession of numbers from which a periodic analogue waveform is produced. These numbers represent a triangular waveform (or a sine waveform). Their direct conversion into analogue form by a digital-to-analogue converter, followed by integration by an integrator produces a distorted analogue waveform SW which when limited by a limiter produces an output pulse waveform with an inaccurate mark/space ratio. A subtraction circuit 2 subtracts each number produced by the digital pulse generator from the previous number, to produce a series of new numbers which represent a pre-distorted waveform. When these new numbers are converted into analogue form, the integration of the resulting waveform by the integrator produces an analogue waveform with clearly defined zero crossings. The output pulse waveform is thereby given a relatively constant mark/space ratio.

Abstract: A circuit arrangement for improving the shape of a data pulse waveform prior to data slicing by correcting a reduction of the high frequency content of the waveform using an adaptive crispening technique. The arrangement includes a high-pass filter (1) connected to an input (8) at which the waveform is applied. The filter (1) separates the high frequency content which is multiplied by an amplitude correcting signal in a multiplier (2). The data pulse waveform signal and the multiplier output are added in an adder (6) to produce a resultant output waveform, which is fed to a data slicer (10). The resultant output waveform is also applied to a peak-to-peak detector (3) via a switch (7) when the latter is closed periodically by a timing circuit (5). The detector (3) produces a control signal proportional to the amplitude of the resultant output waveform which it receives via the switch (7).

Abstract: As shown in FIG. 8, a phase shifter for phase shifting a single frequency clock signal CK as produced by an oscillator (813) comprises an inverter (805) and a delay network (804) for producing phase quadrature versions I.sub.ac, I.sub.ac and Q.sub.ac, Q.sub.ac of the signal. A current generator (803) produces control currents I.sub.c, I.sub.c and Q.sub.c, Q.sub.c, the magnitudes of which are determined by a control voltage V.sub.c whose magnitude represents a required phase shift. Two multipliers (801) and (802) multiply the signal pairs I.sub.ac, I.sub.ac and I.sub.c, I.sub.c ; and the signal pairs Q.sub.ac, Q.sub.ac and Q.sub.c, Q.sub.c, to produce resultant quadrature signals which are combined in an adder (806) to produce the phase shifted clock signal CLK (and CLK). The phase shift range is made to cover a number of cycles by an arrangement comprising two limit detectors (807) and (808), an OR-gate ( 809), a .div.2 circuit (810), and two reversing switches (811) and (812).

Abstract: As shown in FIG. 7, a phase sensitive detector comprises two D-type flip-flops 701 and 702 which are arranged so that in response to data pulses DP and clock pulses CK they produce respective pulse sequences D1 and D2. FIG. 8 shows the relative timing of these pulses and pulse sequences. An exclusive OR-gate 703 receives the pulse sequences D1 and D2, and an exclusive OR-gate 704 receives the pulse sequence D1 and the data pulses DP. The clock pulses CK can be up to one half a clock pulse period late or up to one half a clock pulse period early relative to a desired phase relationship of the clock pulses CK with the data pulses DP. According as the actual relative phase is correct, late or early, the duration of the logic output from the gate 704 will be the same as, proportionately longer than, or proportionately shorter than, the duration of the logic output from the gate 703.

Abstract: A method of and an arrangement for slicing data in the form of a bi-amplitude data pulse signal comprising a sequence of clock pulses followed by a sequence of data pulses. The absolute mean amplitude of the sequence of clock pulses is used as the slicing level for the sequence of data pulses. As shown in FIGS. 3(a) to 3(d) and FIG. 5, the slicing level s is produced by an integrator 22,23 in response to a difference signal v-d'. The signal v is the incoming data pulse signal and the signal d' is a modified sliced data pulse signal which is produced by a multiplier 25. The multiplier 25 is fed by a sliced data pulse signal d and an amplitude correction factor a which is twice the difference between the black level amplitude and the mean of the amplitude of the sequence of clock pulses.

Abstract: In a television receiver adapted for the display of a normal television picture and/or message information in which both separated synchronizing signals and locally derived synchronizing signals are available, the selective use of one or the other of these two forms of synchronizing signals, having regard to different display circumstances, for the picture and message information display.

Abstract: An interface device for selectively accessing two internal signal paths of an integrated circuit through a single external connection pin. Each of the signal paths is provided with a bias voltage sensitive conduction device that permits conduction at a different externally provided bias voltage that inhibits current flow in the other conduction device. The different bias voltages are provided to the external connection pin through an external load resistor.